High speed trellis encoding for discrete multitone transceivers

• US 6,754,283 B1
• Filed: 10/13/2000
• Issued: 06/22/2004
• Est. Priority Date: 10/13/2000
• Status: Expired due to Fees

• Current Assignee: Mindspeed Technologies Inc. (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Mindspeed Technologies Inc. (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Li, Hsiang-Ling
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): WANG, TED M
• Application Number:
  US09/688,258
• Time in Patent Office: 1,348 Days
• Field of Search: 375/130, 375/141, 375/265, 375/150, 375/259, 375/341, 375/298, 375/288, 375/290, 375/261, 714/755, 714/758, 714/792
• US Class Current: 375/265
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 27/2602 Signal structure
• CPC Class Codes: H04L 27/3416 in which the information is carried by both the individual signal points and the subset to which the individual points belong, e.g. using coset coding, lattice coding, or related schemes

Abstract

A three-stage four-dimensional encoding system and method for DMT-based transceivers includes a first stage where a parallel shifter shifts three bits of input data bits from a shadow register into a holding register. Next, a convolutional encoder generates encoded bits v1, v0, w1 and w0, using the three bits in the holding register. The encoded bits w1 and w0 may be registered as w1′ and w0′ for later use. In the second stage, the encoded bits v1 and v0 are provided to the inputs of the parallel shifter for parallel parsing of bits for the first tone of a pair of tones of DMT and the number of bits needed for the first tone are parallel shifted to the holding register. The bits in the holding register are then mapped by a constellation mapper into a constellation point. In the third stage, the encoded bits w1′ and w0′ are provided to the inputs of the parallel shifter for parallel parsing of bits for the second tone of the pair of tones and the number of bits needed for the second tone are parallel shifted to the holding register. The bits in the holding register are then mapped by a constellation mapper into a constellation point.

Claims

1. An encoding system for encoding data bits, said system comprising:

a first register having a plurality of first register inputs and a plurality of first register outputs;

a second register having a plurality of second register inputs and a plurality of second register outputs;

a parallel shifter having a plurality of parallel shifter inputs and a plurality of parallel shifter outputs; and

an encoder;

wherein said data bits are received by said first register inputs, a plurality of said data bits are parallel shifted from said first register outputs through said parallel shifter inputs and said parallel shifter outputs to said second register inputs for use by said encoder.

2. The system of claim 1, wherein said encoder has a plurality of encoder inputs, and said plurality of said data bits are provided by said parallel shifter outputs to said encoder inputs.

3. The system of claim 2, wherein said encoder has a plurality of encoder outputs, and encoded data generated by said encoder are provided to parallel shifter inputs through said encoder outputs.

4. The system of claim 1 further comprising a constellation mapper having a plurality of constellation mapper inputs, wherein said second memory outputs are in communication with a plurality of constellation mapper inputs.

5. The system of claim 1, wherein said encoder is a convolutional encoder.

19. The system of claim 1, wherein said encoder is a convolutional encoder.

6. A four-dimensional trellis encoding method for encoding a first number of bits (b1) in a first tone and a second number of bits (b2) in a second tone, said method comprising the steps of:

moving Rs1 bits of data bits from a first register to a second register if Rs1 is less than three, wherein Rs1 is a number of remaining data bits in said first register;

receiving one or more bits of data bits by said first register after said moving step;

moving (Rs1−

3) bits of said data bits from said first register to a said second register after said receiving step;

generating four convolutionally encoded bits designated by v1,v0,w1,w0 using said data bits in said second register;

receiving one or more bits of said data bits by said first register if D1 is greater than eight, wherein D1 is zero if Rs1′

is greater or equal to b1, else D1 is b1−

Rs1′

, wherein Rs1′

is equal to (Rs1−

3+8+2); and

parallel shifting b1 bits to said second register, wherein said b1 bits include v1, v0 and if said b1 bits are greater than two, said b1 bits further include one or more of said data bits in said first register.

7. The method of claim 6, wherein said receiving steps receive eight bits of said data bits at a time.

8. The method claim 6, wherein said first register is an eight-bit register.

9. The method of claim 6, wherein said second register is a fifteen-bit register.

10. The method of claim 6, wherein said moving is performed by a parallel shifter having ten inputs and twenty-three outputs.

11. A method of encoding data bits to generate final bits, said method comprising the steps of:

receiving a number of first bits of said data bits by a first memory if a number of remaining data bits in said first memory is less than three;

parallel shifting a number of second bits of said data bits from said first memory to a second memory;

generating a number of encoded bits using said second bits;

receiving a number of third bits of said data bits by said first memory based on said number of remaining bits, said number of first bits, said number of second bits, a number of final bits and said number of encoded bits for generating said final bits; and

parallel shifting said final bits to said second memory, wherein said final bits include a portion of said encoded bits and if said final bits are greater than said portion of said encoded bits, said final bits further include one or more of said data bits in said first memory.

12. The method of claim 11, wherein said receiving steps receive a number of bits at a time.

13. The method claim 11, wherein said first memory and said second memory are registers.

14. The method of claim 13, wherein said parallel shifting is performed by a parallel shifter in communication with said registers.

15. A trellis encoding method for DMT-based transceivers, said method comprising:

a first stage including the steps of;

receiving, in a register, first bits for a first tone of a pair of tones;

encoding said first bits to generate first encoded bits;

mapping said first encoded bits into a first constellation point;

a second stage performed after said first stage, said second stage including the steps of;

receiving in said register, second bits for a second tone of said pair of tones;

encoding said second bits to generate second encoded bits; and

mapping said second encoded bits into a second constellation point.

16. An encoding system for encoding data bits, said system comprising:

a first memory having a plurality of first memory inputs and a plurality of first memory outputs;

a second memory having a plurality of second memory inputs and a plurality of second memory outputs;

a parallel shifter having a plurality of parallel shifter inputs and a plurality of parallel shifter outputs; and

an encoder having a plurality of encoder inputs and a plurality of encoder outputs;

wherein said data bits are received by said first memory inputs, a plurality of said data bits are parallel shifted from said first memory outputs through said parallel shifter inputs and said parallel shifter outputs to said second memory inputs for use by said encoder, and wherein said plurality of said data bits are provided by said parallel shifter outputs to said encoder inputs and encoded data generated by said encoder are provided to parallel shifter inputs through said encoder outputs.

17. The system of claim 16 further comprising a constellation mapper having a plurality of constellation mapper inputs, wherein said second memory outputs are in communication with a plurality of constellation mapper inputs.

18. The system of claim 16, wherein said first memory and said second memory are registers.