External resistor and method to minimize power dissipation in DC holding circuitry for a communication system

• US 6,754,341 B2
• Filed: 10/09/2001
• Issued: 06/22/2004
• Est. Priority Date: 04/22/1997
• Status: Expired due to Fees

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Scott, Jeffrey W., Welland, David R., Sooch, Navdeep S.
• Primary Examiner(s): Harvey, Minsun Oh
• Assistant Examiner(s): Swerdlow, Daniel
• Application Number:
  US09/973,254
• Publication Number:
  US 20020018557A1
• Time in Patent Office: 987 Days
• Field of Search: 379/93.05, 379/412, 379/413, 379/393, 379/405
• US Class Current: 379/413
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/06 Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04M 1/573 Line monitoring circuits for detecting caller identification
• CPC Class Codes: H04M 11/06 Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
• CPC Class Codes: H04M 19/001 Current supply source at the exchanger providing current to substations
• CPC Class Codes: H04M 19/02 providing ringing current or supervisory tones, e.g. dialling tone or busy tone
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g. ADCs and DACs) in the CMOS integrated circuit.

Claims

1. A method for reducing power dissipation requirements for a direct access arrangement integrated circuit that is configured to be coupled between the user end of a phone line and an isolation barrier, comprising:

providing a DC holding circuit that is capable of receiving current from phone

generating an internal DC supply voltage for the integrated circuit with said DC holding circuit;

coupling an external power dissipating resistor to power supply circuitry generating said DC supply voltage by connecting the resistor external to a chip interface of the integrated circuit; and

generating a second power supply within the integrated circuit from power transmitted across the isolation barrier,

wherein said coupling step further comprises positioning said power dissipating resistor outside of a current path for said internal DC supply voltage.

2. A method for reducing power dissipation requirements for a direct access arrangement integrated circuit that is configured to be coupled between the user end of a phone line and an isolation barrier, comprising:

providing a DC holding circuit that is capable of receiving current from phone lines;

generating an internal DC supply voltage for the integrated circuit with said DC holding circuit; and

coupling an external power dissipating resistor to power supply circuitry generating said DC supply voltage by connecting the resistor external to a chip interface of the integrated circuit; and

generating a second power supply within the integrated circuit utilizing power transmitted across the isolation barrier, wherein the isolation barrier includes at least one isolation capacitor,

wherein said coupling step further comprises positioning said power dissipating resistor outside of a current path for said internal DC supply voltage.

3. A method for reducing power dissipation requirements for a direct access arrangement integrated circuit that is configured to be coupled between the user end of a phone line and an isolation barrier, comprising:

providing a DC holding circuit that is capable of receiving current from phone lines;

generating an internal DC supply voltage for the integrated circuit with said DC holding circuit; and

coupling an external power dissipating resistor to power supply circuitry generating said DC supply voltage by connecting the resistor external to a chip interface of the integrated circuit; and

generating a clock signal within the integrated circuit utilizing clock information transmitted across the isolation barrier,

wherein said coupling step further comprises positioning said power dissipating resistor outside of a current path for said internal DC supply voltage.