CMOS low noise amplifier

• US 6,754,478 B1
• Filed: 11/13/2000
• Issued: 06/22/2004
• Est. Priority Date: 07/24/1998
• Status: Expired due to Term

• Current Assignee: GCT Semiconductor Incorporated
• Original Assignee: GCT Semiconductor Incorporated
• Inventors: Jeong, Deog-Kyoon, Lee, Kyeongho
• Primary Examiner(s): Vuong, Quochien B.
• Application Number:
  US09/709,314
• Time in Patent Office: 1,317 Days
• Field of Search: 455/232.1, 455/234.1, 455/234.2, 455/241.1, 455/245.1, 455/245.2, 455/250.7, 455/252.1, 455/255, 455/259, 455/260, 330/252, 330/254, 330/259, 330/260, 330/278, 330/277, 330/282, 330/291, 330/295, 330/253
• US Class Current: 455/232.1
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03H 2011/0494 Complex filters
• CPC Class Codes: H03K 9/00 Demodulating pulses which have been modulated with a continuously-variable signal
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 1/403 using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency

Abstract

A CMOS low noise amplifier (LNA) is provided that is formed without inductors. The CMOS LNA can be used for a single-chip CMOS RF receiver. The CMOS LNA can include a plurality of amplification stages coupled between an input terminal and an output terminal and a gain controller coupled to each of the plurality of amplifier stages, wherein the CMOS LNA does not include an inductor. Each of the amplification stages can have a symmetrically configured and sized first and second circuits to increase a dynamic range and a feedback loop.

Claims

1. A CMOS low noise amplifier (LNA), comprising:

a plurality of amplification stages coupled between an input terminal and an output terminal; and

a gain controller coupled to each of the plurality of amplifier stages, wherein each of the amplification stages comprises first and second symmetric circuits, and wherein said each amplification stage has a single input terminal.

2. The CMOS LNA of claim 1, wherein said each of the amplification stages comprises:

a feedback loop coupled between an output node of said each amplification stage and the second symmetric circuit, wherein the second circuit comprises,

first and second NMOS type transistors coupled in series between the output node of the amplification stage and a second prescribed voltage, and

a second capacitor coupled between the second prescribed voltage and a junction coupling the first and second NMOS type transistors.

3. The CMOS LNA of claim 1, wherein the first circuit comprises:

first and second PMOS type transistors coupled in series between a first prescribed voltage and a corresponding output node of the amplification stage; and

a first capacitor coupled between a second prescribed voltage and a junction coupling the first and second PMOS type transistors, wherein the second circuit comprises,

first and second NMOS type transistors coupled in series between the output node of the amplification stage and the second prescribed voltage, and

a second capacitor coupled between the second prescribed voltage and a junction coupling the first and second NMOS type transistors.

4. The CMOS LNA of claim 3, wherein the feedback loop comprises:

a first operational amplifier having an output coupled to a control electrode of the second NMOS type transistor;

a first resistor coupled to the output node of the amplification stage and a first input of the first operational amplifier; and

a third capacitor coupled between the second prescribed voltage and the first input of the operational amplifier, and wherein a second input terminal of the first operational amplifier is coupled to a third prescribed voltage, wherein a level of the third prescribed voltage is between levels of the first and second prescribed voltages.

5. The CMOS LNA of claim 4, further comprising:

a second resistor coupled to the input terminal; and

a fourth capacitor coupled in series between the second resistor and the second prescribed voltage, wherein a junction coupling the second resistor and the fourth capacitor provides the third prescribed voltage.

6. The CMOS LNA of claim 5, wherein the first and second input terminals of the first operational amplifier are the non-inverting and inverting amplifiers, respectively.

7. The CMOS LNA of claim 5, wherein the gain controller comprises:

a gain transistor and a gain current source coupled in series between the first prescribed voltage and the second prescribed voltage; and

a gain capacitor coupled between the second prescribed voltage and a control electrode of the gain transistor, and wherein a control electrode and a second electrode of the gain transistor are coupled together.

8. The CMOS LNA of claim 7, wherein the gain controller and first PMOS type transistors of the amplification stages comprise a current mirror, and wherein the third prescribed voltage is one-half the first prescribed voltage.

9. The CMOS LNA of claim 1, wherein the gain controller comprises:

a gain transistor and a gain current source coupled in series between the first prescribed voltage and the second prescribed voltage; and

a gain capacitor coupled between the second prescribed voltage and a control electrode of the gain transistor, and wherein a control electrode and a second electrode of the gain transistor are coupled together.

10. The CMOS LNA of claim 1, wherein the CMOS LNA is formed on a single chip, and wherein the CMOS LNA receives an input RF signal in a range of approximately 1.8 GHz-2.4 GHz.

11. The CMOS LNA of claim 1, wherein each symmetric circuit comprises:

first and second transistors coupled in series between a prescribed voltage and an output node of the corresponding amplification stage; and

a capacitor coupled to a junction connecting the first and second transistors.

12. The CMOS LNA of claim 1, wherein each symmetric circuit is connected to the single input terminal.

13. The CMOS LNA of claim 1, wherein the CMOS LNA does not include a spiral inductor.

14. An amplification stage for a low noise amplifier (LNA), comprising:

first and second circuits coupled between an input node and an output node, wherein the first and second circuits have a symmetric configuration, wherein each of the first and second symmetric circuits is configured to receive a single input; and

a feedback loop coupled between the output node and the second circuit.

15. The amplification stage of claim 14, wherein the first circuit comprises:

first and second PMOS type transistors coupled in series between a first prescribed voltage and the output node of the amplification stage; and

a first capacitor coupled between a second prescribed voltage and a junction coupling the first and second PMOS type transistors, wherein the second circuit comprises,

first and second NMOS type transistors coupled in series between the output node of the amplification stage and the second prescribed voltage, and

a second capacitor coupled between the second prescribed voltage and a junction coupling the first and second NMOS type transistors, wherein the first and second circuits are symmetric.

16. The amplification stage of claim 14, wherein the feedback loop comprises:

a first operational amplifier having an output coupled to a control electrode of the second NMOS type transistor;

a first resistor coupled to the output node of the amplification stage and a first input of the first operational amplifier; and

a third capacitor coupled between the second prescribed voltage and the first input of the operational amplifier, and wherein a second input terminal of the first operational amplifier is coupled to a third prescribed voltage, wherein a level of the third prescribed voltage is between levels of the first and second prescribed voltages.

17. The amplification stage of claim 16, wherein the amplification stage is on a single chip and does not use a spiral inductor.

18. A CMOS low noise amplifier (LNA), comprising:

a first amplifier stage that receives an input RF signal, wherein the first amplifier stage includes first and second symmetric networks and a feedback loop;

a second amplifier stage coupled to an output node of the first amplifier stage, wherein the second amplifier stage includes the first and second symmetric networks and the feedback loop, wherein each of the first and second symmetric networks is configured to receive a single input; and

a gain controller coupled to each of the first symmetric networks of the first and second amplifier stages, wherein the second amplifier stage transmits an amplified RF;

output signal responsive to a control signal of the gain controller.

19. The CMOS LNA of claim 18, wherein said each of the first and second symmetric networks is configured to receive the same single input.

20. The CMOS LNA of claim 19, wherein the first symmetric network comprises:

first and second first-conduction type transistors coupled in series between a first prescribed voltage and a corresponding output node of the amplification stage; and

a first capacitor coupled between a second prescribed voltage and a junction coupling the first and second first-conduction type transistors, wherein the second symmetric network comprises,

first and second second-conduction type transistors coupled in series between the output node of the amplification stage and the second prescribed voltage, and

a second capacitor coupled between the second prescribed voltage and a junction coupling the first and second second-conduction type transistors.

21. An RF communication system, comprising:

an antenna that receives RF signals having a carrier frequency;

a phase lock loop that generates a local oscillator signal;

a RF filter coupled to the antenna that filters the received RF signals;

a demodulation mixer that mixes the filtered received RF signals with the local oscillator to output demodulated signals having a frequency reduced by the local oscillator;

a modulation mixer that mixes the local oscillator signals with transmission data to modulate the transmission data;

a power amplifier that amplifies the modulated transmission data and transmits the data to the antenna for transmission; and

a CMOS low noise amplifier (LNA) coupled between the RF filter and the demodulation mixer that amplifies the filtered RF signals, wherein the CMOS LNA comprises,

a plurality of amplification stages coupled between an input terminal and an output terminal, and

a gain controller coupled to each of the plurality of amplifier stages, wherein each of the amplification stages comprises,

first and second symmetric circuits, wherein each of the first and second symmetric circuits comprise a transistor directly connected to a prescribed capacitor, and

a feedback loop coupled between an output node of said each amplification stage and the second symmetric circuit.

22. The RF communication system of claim 21, wherein the first symmetric circuit comprises:

first and second PMOS type transistors coupled in series between a first prescribed voltage and a corresponding output node of the amplification stage; and

a first capacitor coupled between a second prescribed voltage and a junction coupling the first and second PMOS type transistors, wherein the second symmetric circuit comprises,

first and second NMOS type transistors coupled in series between the output node of the amplification stage and the second prescribed voltage, and

a second capacitor coupled between the second prescribed voltage and a junction coupling the first and second NMOS type transistors.

23. The RF communication system of claim 21, wherein each symmetric circuit is connected to a single input terminal.

24. The RF communication system of claim 23, wherein each symmetric circuit comprises:

first and second transistors coupled in series between a prescribed voltage and an output node of the corresponding amplification stage; and

a capacitor coupled to a junction connecting the first and second transistors.

25. A CMOS low noise amplifier (LNA), comprising:

a plurality of amplification stages coupled between an input terminal and an output terminal;

a gain controller coupled to each of the plurality of amplifier stages, wherein each of the amplification stages comprises first and second symmetric circuits; and

a feedback loop coupled between an output node of said each amplification stage and the second symmetric circuit, wherein said first circuit comprises,

first and second first-conduction type transistors coupled in series between a first prescribed voltage and a corresponding output node of the amplification stage, and

a first capacitor coupled between a second prescribed voltage and a junction coupling the first and second first-conduction type transistors, wherein the second circuit comprises,

first and second second-conduction type transistors coupled in series between the output node of the amplification stage and the second prescribed voltage, and

a second capacitor coupled between the second prescribed voltage and a junction coupling the first and second second-conduction type transistors.

26. A CMOS low noise amplifier (LNA) comprising:

a plurality of amplification stages coupled between an input terminal and an output terminal; and

a gain controller coupled to each of the plurality of amplifier stages, wherein the CMOS LNA does not include a spiral inductor, and wherein the gain controller comprises,

a gain transistor and a gain current source coupled in series between a first prescribed voltage and a second prescribed voltage, and

a gain capacitor coupled between the second prescribed voltage and a control electrode of the gain transistor, and wherein a control electrode and a second electrode of the gain transistor are coupled together.

27. An amplification stage for a low noise amplifier (LNA), comprising:

first and second circuits coupled between an input node and an output node, wherein the first and second circuits have a symmetric configuration; and

a feedback loop coupled between the output node and the second circuit, wherein the feedback loop comprises,

a first operational amplifier having an output coupled to a control electrode of transistor,

a first resistor coupled to the output node of the amplification stage and a first input of the first operational amplifier, and

a capacitor coupled between a second prescribed voltage and the first input of the operational amplifier, and wherein a second input terminal of the first operational amplifier is coupled to a third prescribed voltage, wherein a level of the third prescribed voltage is between levels of a first prescribed voltage and the second prescribed voltage.