Squaring circuit and electronic device using same

• US 6,754,479 B1
• Filed: 05/30/2000
• Issued: 06/22/2004
• Est. Priority Date: 05/30/2000
• Status: Expired due to Fees

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hughes, James David, Oakley, John Richard
• Primary Examiner(s): Urban, Edward F.
• Assistant Examiner(s): Jackson, Blane J.
• Application Number:
  US09/583,645
• Time in Patent Office: 1,484 Days
• Field of Search: 455/234.1, 455/245.1, 455/232.1, 455/240.1, 375/345
• US Class Current: 455/245.1
• CPC Class Codes: H03G 3/3068 Circuits generating control signals for both R.F. and I.F. stages
• CPC Class Codes: H03G 7/007 of digital or coded signals

Abstract

An electronic device (1100) includes squaring circuit (1500) that includes a logarithmic compression function (1510), a squaring function (1525), a doubling function (1595), and a logarithmic decompression function (1590). The logarithmic compression function (1510) accepts a binary input (1505) of width W and value X, and produces an output having a binary power component (1520) and a binary magnitude component (1515). The squaring function (1525) generates an adjusted squared magnitude component (1542) and a selection signal (1561). The doubling function (1595) generates a doubled power component (1556). The logarithmic decompression function (1565) generates an approximate squared output (1570) of width 2W from the doubled power and adjusted squared magnitude components (1556, 1542). The approximate squared output (1570) has a value that approximates the square of X to a predetermined amount of precision, N.

Claims

1. A squaring circuit, comprising:

a logarithmic compression function that accepts a binary input of width W and value X, and produces an output having a binary power component having a value of POWER, and a binary magnitude component having a value of MAGNITUDE, wherein POWER and MAGNITUDE together represent X to a predetermined amount of precision, N;

a squaring function that generates an adjusted squared magnitude component and a selection signal from MAGNITUDE;

a doubling function that generates a doubled power component based on POWER and the selection signal; and

a logarithmic decompression function that generates an approximate squared output of width 2W from the doubled power and adjusted squared magnitude components,

wherein the approximate squared output has a value that approximates the square of X to the predetermined amount of precision that is less than or equal to 2N.

2. The squaring circuit according to claim 1, wherein the logarithmic compression and decompression functions are Mu-law type functions.

3. The squaring circuit according to claim 1, wherein the logarithmic compression function comprises:

a power function that generates the power component as

POWER=int(log₂(X)); and

a magnitude function that generates the magnitude component as

MAGNITUDE=int(X*2^(N-POWER))−

2^N,

wherein N is an integer that specifies a number of bits of the precision to which X is approximated.

4. The squaring circuit according to claim 1, wherein the doubling function comprises a left shift function that generates a doubled power signal by shifting the binary power component 1 bit left.

5. The squaring circuit according to claim 1, wherein the squaring function comprises an exact square function that generates an exact square signal of an augmented magnitude input, the augmented input comprising the binary magnitude component augmented by a high order bit.

6. The squaring circuit according to claim 5, wherein the exact square function comprises a lookup table.

7. The squaring circuit according to claim 5, wherein the squaring function further comprises a steering circuit coupled to the exact square function, the steering circuit comparing the exact square to a binary value of 2^(2N+1) and generating a steering signal from the result of the comparison.

8. The squaring circuit according to claim 5, wherein the squaring function further comprises an adjustment function that generates the adjusted squared magnitude component from the exact square signal, the adjusted squared magnitude component having a precision of N bits.

9. The squaring circuit according to claim 5, wherein the squaring function further comprises:

a first integer-divider that performs an integer operation on the result of a division of the exact square by 2^N;

a second integer-divider that performs an integer operation on the result of a division of the exact square by (2^(N+1)); and

a multiplexer that selects an output of one of the first and second integer-dividers according to a state of a steering signal.

10. The squaring circuit according to claim 5, wherein the doubling function comprises:

a doubler that generates a doubled power signal having a value double that of POWER;

an adder that generates an augmented doubled power by adding a binary one to the value of the doubled power signal; and

a multiplexer that generates the doubled power component by selecting one of the doubled power signal and augmented doubled power signal according to a state of a steering signal.

11. The squaring circuit according to claim 1, wherein the squaring function generates the adjusted squared magnitude component having value ADJSQMAG, and the doubling function generates the doubled power component having value DBLPOWER, as:

When (MAGNITUDE+2^N)²>

=2^(2N+1),

ADJSQMAG=N least significant bits of

int(((MAGNITUDE+2^N)²)*2<sup>−

(N+1)</sup>) and

DBLPOWER=2*POWER+1;

When (MAGNITUDE+2^N)²<

2^(2N+1),

ADJSQMAG=N least significant bits of

int(((MAGNITUDE+2^N)²)*2<sup>−

N</sup>) and

DBLPOWER=2*POWER.

12. The squaring circuit according to claim 1, wherein the logarithmic decompression function generates the approximate squared output from a value, ADJSQMAG, of the adjusted squared magnitude component, and from a value, DBLPOWER of the doubled power component, as:

(ADJSQMAG+2^N)*2^(DBLPOWER-N).

13. An electronic device comprising the squaring circuit according to claim 1.

14. An automatic gain control (AGC) system for a radio frequency (RF) receiver, comprising:

a magnitude generator that generates a binary voltage squared signal having a binary value that is directly proportional to a recovered signal power of an intercepted signal; and

a gain corrector that determines a gain control value adjustment as a multiple of increments that are approximately 3 decibel (dB), by shifting a first value by a plurality of bits and comparing the shifted first value to a second value, wherein each of the first and second values are one of the binary voltage squared signal and a predetermined threshold, and wherein the magnitude generator comprises;

a logarithmic compression function that accepts a binary input of width W and value X, and produces an output having a binary power component having a value of POWER, and a binary magnitude component having a value of MAGNITUDE, wherein POWER and MAGNITUDE together represent X to an predetermined amount of precision, N;

a squaring function that generates an adjusted squared magnitude component and a selection signal from MAGNITUDE;

a doubling function that generates a doubled power component based on POWER and the selection signal; and

a logarithmic decompression function that generates an approximate squared output of width 2W from the doubled power and adjusted squared magnitude components,

wherein the approximate squared output has a value that approximates the square of X to a predetermined amount of precision, N.