Mobile communication device having dual micro processor architecture with shared digital signal processor and shared memory

• US 6,754,509 B1
• Filed: 12/30/1999
• Issued: 06/22/2004
• Est. Priority Date: 12/30/1999
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Ludwin, Albert Scott, Iraninejad, Mehraban, Jha, Sanjay, Khan, Safi, Lee, Chauhung, Sankuratri, Raghu, Higgins, Richard, Yu, Nicholas K.
• Primary Examiner(s): Maung, Nay
• Assistant Examiner(s): NGUYEN, TU X
• Application Number:
  US09/475,336
• Time in Patent Office: 1,636 Days
• Field of Search: 455/550, 455/556, 455/450, 455/466, 455/452, 455/556.2, 455/556.1, 710/244, 710/308, 380/49
• US Class Current: 455/556.1
• CPC Class Codes: H04B 1/3805 with built-in auxiliary receivers
• CPC Class Codes: H04M 1/72403 with means for local support of applications that increase the functionality

Abstract

The dual microprocessor system includes one microprocessor configured to perform wireless telephony functions and another configured to perform personal digital assistant (PDA) functions and other non-telephony functions. A memory system and a digital signal processor (DSP) are shared by the microprocessors. By providing a shared memory system, data required by both data microprocessors is conveniently available to both of the microprocessors and their peripheral components thereby eliminating the need to provide separate memory subsystems and further eliminating the need to transfer data back and forth between the separate memory subsystems. By providing a shared DSP, separate DSP devices need not be provided, yet both microprocessors can take advantage of the processing power of the DSP. In a specific example described herein, the microprocessors selectively program the DSP to perform, for example, vocoder functions, voice recognition functions, handwriting recognition functions, and the like.

Claims

1. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared memory system accessible by each of said plurality of microprocessors;

wherein the plurality of microprocessors includes a first microprocessor and a second microprocessor;

wherein said shared memory system includes a set of shared registers for storing commands, with each respective microprocessor communicating with the other microprocessor by storing commands within said shared registers for retrieval by the other microprocessor.

2. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared memory system accessible by each of said plurality of microprocessors;

The system of claim 1 wherein the plurality of microprocessors includes a first microprocessor and a second microprocessor;

wherein said shared memory system includes a set of shared registers for storing commands, with each respective microprocessor communicating with the other microprocessor by storing commands within said shared registers for retrieval by the other microprocessor;

further including an interrupt system, with each respective microprocessor forwarding an interrupt to the other microprocessor after a command has been stored within said shared registers to notify the other microprocessor that a command is available for retrieval.

3. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared memory system accessible by each of said plurality of microprocessors;

wherein the plurality of microprocessors includes a first microprocessor and a second microprocessor;

further including a shared digital signal processor accessible by both said first and second microprocessors;

wherein said shared digital signal processor includes shared program memory for storing firmware for controlling the functionality of the digital signal processing, with each respective microprocessor determining whether the digital signal processor is available and, if so, selectively storing firmware within the digital signal processor.

4. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared memory system accessible by each of said plurality of microprocessors,

wherein the plurality of microprocessors includes a first microprocessor and a second microprocessor;

further including a shared digital signal processor accessible by both said first and second microprocessors;

wherein said shared digital signal processor includes shared program memory for storing firmware for controlling the functionality of the digital signal processing, with each respective microprocessor determining whether the digital signal processor is available and, if so, selectively storing firmware within the digital signal processor;

wherein said firmware controls the digital signal processor to perform functions wherein the functions are vocoder functions, GPS functions, voice recognition functions, or handwriting recognition functions.

5. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared memory system accessible by each of said plurality of microprocessors,

wherein the plurality of microprocessors includes a first microprocessor and a second microprocessor;

further including a shared digital signal processor accessible by both said first and second microprocessors;

wherein said shared digital signal processor includes shared program memory for storing firmware for controlling the functionality of the digital signal processing, with each respective microprocessor determining whether the digital signal processor is available and, if so, selectively storing firmware within the digital signal processor;

for wherein the mobile communication device is a cellular telephone and wherein said firmware controls the digital signal processor to perform filtering functions to detect a nearest base station to the cellular telephone.

6. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared memory system accessible by each of said plurality of microprocessors;

wherein the plurality of microprocessors includes a first microprocessor and a second microprocessor;

wherein the first and second microprocessors are driven by first and second clock signals, of potentially differing clock rates, and wherein said a shared memory system is driven by a clock signal set to the same rate as the higher clock rate of the first and second clock signals.

7. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared memory system accessible by each of said plurality of microprocessors;

wherein the plurality of microprocessors includes a first microprocessor and a second microprocessor;

wherein the first and second microprocessors are driven by first and second clock signals, of potentially differing clock rates, and wherein said a shared memory system is driven by a clock signal set to the same rate as the higher clock rate of the first and second clock signals;

wherein said clock signal of said shared memory is within an independent clock regime from that of said clock signals of said first and second microprocessors such that said shared memory operates even if one or both of the first and second clock signals are deactivated.

8. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared memory system accessible by each of said plurality of microprocessors;

wherein the plurality of microprocessors includes a first microprocessor and a second microprocessor;

further including a first non-shared memory system connected to the first, microprocessor and a first direct memory access unit interconnecting the first non-shared memory system and the shared memory system.

9. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared memory system accessible by each of said plurality of microprocessors;

wherein the plurality of microprocessors includes a first microprocessor and a second microprocessor;

further including a first non-shared memory system connected to the first microprocessor and a first direct memory access unit interconnecting the first non-shared memory system and the shared memory system;

further including a shared digital signal processor accessible by both said first and second microprocessors, said direct memory access system additionally interconnected to the shared digital signal processor.

10. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared memory system accessible by each of said plurality of microprocessors;

wherein the plurality of microprocessors includes a first microprocessor and a second microprocessor;

further including a first non-shared memory system connected to the first microprocessor and a first direct memory access unit interconnecting the first non-shared memory system and the shared memory system;

further including a second non-shared memory system connected to the second microprocessor and a second direct memory access unit interconnecting the second non-shared memory system and the shared memory system.

11. A system for use in a mobile communications device, system comprising:

a plurality of microprocessors; and

a shared digital signal processor accessible by each of said plurality of microprocessors;

wherein the plurality of the microprocessors includes first and second microprocessors;

wherein said shared digital signal processor includes shared program memory for storing firmware for controlling the functionality of the digital signal processing, with each respective microprocessor determining whether the digital signal processor is available and, if so, selectively storing firmware within the digital signal processor.

12. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared digital signal processor accessible by each of said plurality of microprocessors;

wherein the plurality of the microprocessors includes first and second microprocessors;

wherein said shared digital signal processor includes shared program memory for storing firmware for controlling the functionality of the digital signal processing, with each respective microprocessor determining whether the digital signal processor is available and, if so, selectively storing firmware within the digital signal processor;

wherein said firmware controls the digital signal processor to perform functions wherein the functions are vocoder functions, GPS functions, voice recognition functions, or handwriting recognition functions.

13. A system for use in a mobile communications device, said system comprising:

a plurality of microprocessors; and

a shared digital signal processor accessible by each of said plurality of microprocessors;

wherein the plurality of the microprocessors includes first and second microprocessors;

wherein said shared digital signal processor includes shared program memory for storing firmware for controlling the functionality of the digital signal processing, with each respective microprocessor determining whether the digital signal processor is available and, if so, selectively storing firmware within the digital signal processor;

for wherein the mobile communication device is a cellular telephone and wherein said firmware controls the digital signal processor to perform filtering functions to detect a nearest base station to the cellular telephone.

14. A system for use in a mobile communications device, the system comprising:

a plurality of microprocessors including a first microprocessor and a second microprocessor, wherein the first microprocessor is configured for controlling cellular telephony functions and the second microprocessor is configured for controlling personal data assistant functions; and

a shared memory system accessible by each of the plurality of microprocessors, wherein the shared memory system includes a set of shared registers for storing commands, with each respective microprocessor communicating with the other microprocessor by storing commands within the shared registers for retrieval by the other microprocessor.

15. The system of claim 14 further including an interrupt system, with each respective microprocessor forwarding an interrupt to the other microprocessor after a command has been stored within the shared registers to notify the other microprocessor that a command is available for retrieval.

16. A system for use in a mobile communications device, the system comprising:

a plurality of microprocessors including a first microprocessor and a second microprocessor, wherein the first microprocessor is configured for controlling cellular telephony functions and the second microprocessor is configured for controlling personal data assistant functions; and

a shared memory system accessible by each of the plurality of microprocessors, wherein the shared memory system includes a set of shared registers for storing commands, with each respective microprocessor communicating with the other microprocessor by storing commands within the shared registers for retrieval by the other microprocessor;

wherein the first and second microprocessors are driven by first and second clock signals, of potentially differing clock rates, and wherein the shared memory system is driven by a clock signal set to the same rate as the higher clock rate of the first and second clock signals.

17. A system for use in a mobile communications device, the system comprising:

a plurality of microprocessors including a first microprocessor and a second microprocessor, wherein the first microprocessor is configured for controlling cellular telephony functions and the second microprocessor is configured for controlling personal data assistant functions; and

a shared memory system accessible by each of the plurality of microprocessors, wherein the shared memory system includes a set of shared registers for storing commands, with each respective microprocessor communicating with the other microprocessor by storing commands within the shared registers for retrieval by the other microprocessor;

wherein the first and second microprocessors are driven by first and second clock signals, of potentially differing clock rates, and wherein the shared memory system is driven by a clock signal set to the same rate as the higher clock rate of the first and second clock signals;

wherein the clock signal of the shared memory is within an independent clock regime from that of the clock signals of the first and second microprocessors such that the shared memory operates even if one or both of the first and second clock signals are deactivated.

18. A system for use in a mobile communications device, the system comprising:

a plurality of microprocessors including a first microprocessor and a second microprocessor, wherein the first microprocessor is configured for controlling cellular telephony functions and the second microprocessor is configured for controlling personal data assistant functions; and

a shared digital signal processor accessible by each of the plurality of microprocessors, wherein the shared digital signal processor includes shared program memory for storing firmware for controlling the functionality of the digital signal processing, with each respective microprocessor determining whether the digital signal processor is available and, if so, selectively storing firmware within the digital signal processor.

19. The system of claim 18, wherein the firmware controls the digital signal processor to perform functions wherein the functions are vocoder functions, GPS functions, voice recognition functions, or handwriting recognition functions.

20. The system of claim 18 wherein the mobile communications device is a cellular telephone and wherein the firmware controls the digital signal processor to perform filtering functions to detect a nearest base station to the cellular telephone.