High resolution time-to-digital converter

• US 6,754,613 B2
• Filed: 09/16/2002
• Issued: 06/22/2004
• Est. Priority Date: 03/17/2000
• Status: Expired due to Term

• Current Assignee: Zarbana Digital Fund LLC (Intellectual Ventures LLC)
• Original Assignee: Vector 12 Corporation
• Inventors: Tabatabaei, Sassan, Ivanov, Andre
• Primary Examiner(s): Barlow, John
• Assistant Examiner(s): Lau, Tung
• Application Number:
  US10/244,085
• Publication Number:
  US 20030098731A1
• Time in Patent Office: 645 Days
• Field of Search: 702/189, 327/160, 331/57, 377/25, 377/52, 377/2, 369/45, 370/464, 324/142, 362/187, 455/9, 368/29, 709/207
• US Class Current: 702/189
• CPC Class Codes: G04F 10/00 Apparatus for measuring unknown time intervals by electric means
• CPC Class Codes: G04F 10/06 by measuring phase G04F10/005 takes precedence

Abstract

A time to digital converter (TDC) has a pair of digital oscillators. The periods of the oscillators differ by T_Δ. The oscillators are triggered by START and STOP pulses. A counter counts a number of pulses until reference points on the signals output by the oscillators coincide. Measurements may be made using a dual resolution method. Intrinsic jitter of the TDC can be determined by comparing sets of measurements in which the switch in resolutions is made at different points. A range extender circuit may be provided to extend a valid measurement range of the TDC.

Claims

1. A time to digital converter comprising:

a timing circuit comprising first and second digital oscillators producing first and second clock signals respectively, the first and second oscillators having different periods;

at least one of the oscillators comprising a plurality of controllable delay elements, the delay elements, when activated, altering the period of the oscillator;

a coincidence detector connected to generate a coincidence signal when a reference point in the first clock signal has a known time relationship to a corresponding reference point on the second clock signal;

a first counter connected to count a number, N, of cycles of the first oscillator until the coincidence detector generates the coincidence signal; and

,

a resolution adjustment circuit connected to start the first and second oscillators at times separated by a known interval, compare the number N to a threshold and, if N is not at least equal to a threshold value altering the period of at least one of the oscillators by activating or deactivating one or more of the controllable delay elements.

2. The time to digital converter of claim 1 wherein the timing circuit has a plurality of states including a first state wherein a difference in periods of the first and second signals is T_Δ

1 and a second state wherein a difference in periods of the first and second signals is T<sub>Δ

2</sub> where T<sub>Δ

2</sub><

T<sub>Δ

1</sub>; and

,

the time to digital converter comprises;

a resolution switching control circuit configured to switch the timing circuit between its states; and

,

a second counter connected to count a number (N_C) of edges of the first signal between a START signal and a time when the timing circuit is switched away from its first state;

wherein the first counter is connected to count a number (N_F) of edges of the first signal between a time when the timing circuit is switched to its second state and the time when the coincidence signal is generated.

3. The time to digital converter of claim 2 wherein the resolution switching control circuit comprises a delay element connected to provide a delayed first clock signal and a coincidence detector connected to generate a coincidence signal when a reference point in the second clock signal has a known time relationship to a corresponding reference point on the delayed first clock signal.

4. The time to digital converter of claim 3 wherein the delay element of the resolution switching control circuit is selectively configurable to provide one of at least two different delays.

5. The time to digital converter of claim 3 wherein the delay element comprises a multiplexer connected to a plurality of signal path segments, at least one of the second signal path segments comprising at least one gate, the delayed first clock signal passing through one of the signal path segments selected by the multiplexer.

6. The time to digital converter of claim 3 comprising a range extender circuit, the range extender circuit suppressing the coincidence signal until corresponding edges of the first and second clock signals are within one period of the second clock signal relative to one another.

7. The time to digital converter of claim 6 wherein the range extender circuit is configured to suppress the coincidence signal until no other edges of the first and second clock signals lie between the corresponding edges of the first and second clock signals.

8. The time to digital converter of claim 3 comprising a range extender circuit, the range extender circuit suppressing the coincidence signal until corresponding edges of the first and second clock signals are within one half period of the second clock signal relative to one another.

9. The time to digital converter of claim 8 wherein the delay element is selectively configurable to provide one of at least two different delays.

10. The time to digital converter of claim 8 wherein the delay element comprises a multiplexer connected to a plurality of signal path segments, at least one of the second signal path segments comprising at least one gate, the delayed first clock signal passing through one of the signal path segments selected by the multiplexer.

11. The time to digital converter of claim 3 wherein each of the oscillators comprises a plurality of controllable delay elements.

12. The time to digital converter of claim 11 wherein, in each of the oscillators, the plurality of controllable delay elements comprises a series of digitally controllable delay elements wherein an I^th one of the delay elements provides a delay which is controllably variable by an amount τ

_CDE(I) where τ

_CDE(I) for the delay elements in the series of digitally controllable delay elements are related to one another by τ

_CDE(I)=(1+ξ

)τ

_CDE(I-1) where ξ

is a real number with 1<

(1+ξ

)<

2 and I is an index which identifies the delay elements in the series.

13. The time to digital converter of claim 2 comprising a range extender circuit, the range extender circuit suppressing the coincidence signal until corresponding edges of the first and second clock signals are within one cycle of the second clock relative to one another.

14. The time to digital converter of claim 13 wherein the range extender circuit comprises a first counter connected to count edges of the first signal, a second counter connected to count edges of the second signal and a comparator connected to compare outputs of the first and second counters and the range extender circuit generates a valid range signal when a pulse at the comparator output exceeds a predetermined width.

15. The time to digital converter of claim 14 wherein the first and second counters each comprise a binary counter.

16. The time to digital converter of claim 14 wherein the predetermined width is determined by a delay element coupled between an output of the comparator and a flip flop.

17. The time to digital converter of claim 14 wherein the predetermined width is determined by a delay element coupled between the first clock signal and an input to the first binary counter.

18. The time to digital converter of claim 2 wherein the first and second oscillators comprise ring oscillators each comprising a closed signal path defined at least in part by a plurality of series-connected delay elements each having an input and an output.

19. The time to digital converter of claim 18 wherein the controllable delay elements each comprise a logic gate having an input and output connected in the signal path and a variable load element connected to the output.

20. The time to digital converter of claim 19 wherein the variable load element comprises a tri-state device having an input connected to the output of the logic gate.

21. The time to digital converter of claim 18 wherein each of the oscillators comprises a plurality of digitally controllable delay elements.

22. The time to digital converter of claim 21 wherein, in each of the oscillators, the plurality of digitally controllable delay elements comprises a series of digitally controllable delay elements wherein an I^th one of the delay elements provides a delay which is controllably variable by an amount τ

_CDE(I) where τ

_CDE(I) for the delay elements in the series of digitally controllable delay elements are related to one another by τ

_CDE(I)=(1+ξ

)τ

_CDE(I-1) where ξ

is a number with 1<

(1+ξ

)<

2 and I is an index which identifies the delay elements in the series.

23. The time to digital converter of claim 2 wherein each of the oscillators comprises a plurality of digitally controllable delay elements.

24. The time to digital converter of claim 23 wherein, in each of the oscillators, the plurality of digitally controllable delay elements comprises a series of digitally controllable delay elements wherein an I^th one of the delay elements provides a delay which is controllably variable by an amount τ

_CDE(I) where τ

_CDE(I) for the delay elements in the series of digitally controllable delay elements are related to one another by τ

_CDE(I)=(1+ξ

)τ

_CDE(I-1) where ξ

is a number with 1<

(1+ξ

)<

2 and I is an index which identifies the delay elements in the series.

25. The time to digital converter of claim 1 comprising a range extender circuit, the range extender circuit suppressing the coincidence signal until corresponding edges of the first and second clock signals are within one period of the second clock signal relative to one another.

26. The time to digital converter of claim 24 wherein the range extender circuit comprises a first counter connected to count edges of the first signal, a second counter connected to count edges of the second signal and a comparator connected to compare outputs of the first and second counters.

27. The time to digital converter of claim 25 wherein the range extender circuit comprises first and second memory elements connected to receive a signal from the comparator, and one or more delay elements connected to delay the application of the signal from the comparator to the second memory element relative to the application of the signal from the comparator to the first memory element.

28. The time to digital converter of claim 1 comprising a range extender circuit, the range extender circuit suppressing the coincidence signal until corresponding edges of the first and second clock signals are within one half period of the second clock signal relative to one another.

29. The time to digital converter of claim 6 wherein the range extender circuit comprises a first binary counter connected to count edges of the first signal, a second binary counter connected to count edges of the second signal and a comparator connected to compare outputs of the first and second binary counters and the range extender circuit generates a range valid signal when a pulse at the comparator output exceeds a predetermined width.

30. The time to digital converter of claim 29 wherein the predetermined width is determined by a delay element coupled between an output of the comparator and a flip flop.

31. The time to digital converter of claim 29 wherein the predetermined width is determined by a delay element coupled between the first clock signal and an input to the first binary counter.

32. The time to digital converter of claim 6 wherein each of the oscillators comprises a plurality of digitally controllable delay elements.

33. The time to digital converter of claim 32 wherein, in each of the oscillators, the plurality of digitally controllable delay elements comprises a series of digitally controllable delay elements wherein an I^th one of the delay elements provides a delay which is controllably variable by an amount τ

_CDE(I) where τ

_CDE(I) for the delay elements in the series of digitally controllable delay elements are related to one another by τ

_CDE(I)=(1+ξ

)τ

_CDE(I-1) where ξ

is a number with 1<

(1+ξ

)<

2 and I is an index which identifies the delay elements in the series.

34. The time to digital converter of claim 1 wherein the first and second oscillators comprise ring oscillators each comprising a closed signal path defined at least in part by a plurality of series-connected delay elements each having an input and an output.

35. The time to digital converter of claim 34 wherein the controllable delay elements each comprise a gate having an input and output connected in the signal path and a variable load element connected to the output.

36. The time to digital converter of claim 35 wherein the variable load element comprises a tri-state device having an input connected to the output of the gate.

37. The time to digital converter of claim 36 wherein the tri-state device comprises a tri-NOT gate.

38. The time to digital converter of claim 34 wherein the load element comprises a capacitor connected in series between the output of the gate and a digital switch.

39. The time to digital converter of claim 38 wherein the capacitor comprises an NMOS gate capacitor having a gate electrode connected to the output of the gate.

40. The time to digital converter of claim 38 wherein each of the plurality of controllable delay elements, when activated, affect a period of a corresponding oscillator and wherein activation of each of the plurality of controllable delay elements provides substantially the same effect on the period of the corresponding oscillator.

41. The time to digital converter of claim 38 wherein, in each of the oscillators, the plurality of controllable delay elements comprises a series of digitally controllable delay elements wherein an I^th one of the delay elements provides a delay which is controllably variable by an amount τ

_CDE(I) where τ

_CDE(I) for the delay elements in the series of digitally controllable delay elements are related to one another by τ

_CDE(I)=(1+ξ

)τ

_CDE(I-1) where ξ

is a number with 1<

(l+t)<

2 and I is an index which identifies the delay elements in the series.

42. The time to digital converter of claim 1 wherein each of the oscillators comprises a plurality of digitally controllable delay elements.

43. The time to digital converter of claim 42 comprising a state machine having outputs connected to control each of the plurality of digitally controllable delay elements.

44. A time to digital converter comprising:

a timing circuit comprising first and second digital oscillators producing first and second clock signals respectively, the timing circuit switchable between a plurality of states including a first state wherein a difference in periods of the first and second signals is T<sub>Δ

1</sub> and a second state wherein a difference in periods of the first and second signals is T<sub>Δ

2</sub> where T<sub>Δ

2</sub><

T<sub>Δ

1</sub>;

a resolution switching control circuit connected to switch the timing circuit between its states when a reference point of the first clock signal approaches a first predetermined time relationship with a corresponding reference point of the second clock signal;

a coincidence detector connected to generate a coincidence signal when the reference point in the first clock signal has a second predetermined time relationship to the corresponding reference point on the second clock signal;

a first counter connected to count a number (N_F) of edges of the first clock signal between a time when the timing circuit is switched into its second state and the time when the coincidence signal is generated; and

, a second counter connected to count a number (N_C) of edges of the first signal between a START signal and a time when the timing circuit is switched out of its first state.

45. The time to digital converter of claim 44 wherein the resolution switching control circuit comprises a delay element connected to provide a delayed first clock signal and a coincidence detector connected to generate a resolution switching control signal when the reference point in the second clock signal has a predetermined time relationship to a corresponding reference point on the delayed first clock signal.

46. The time to digital converter of claim 45 wherein the delay element has a first state resulting in a first delay of the delayed first clock signal and a second state resulting in a second delay of the delayed first clock signal different from the first delay.

47. The time to digital converter of claim 46 comprising a range extender circuit, the range extender circuit suppressing the coincidence signal until corresponding reference points of the first and second clock signals are within one period of the second clock signal relative to one another.

48. The time to digital converter of claim 47 wherein the reference points are corresponding signal edges and the range extender circuit is configured to suppress the coincidence signal until no other edges of the first and second clock signals lie between the corresponding edges of the first and second clock signals.

49. The time to digital converter of claim 47 wherein:

the range extender circuit comprises a first counter connected to count reference points of the first signal, a second counter connected to count reference points of the second signal and a comparator connected to compare outputs of the first and second counters; and

,

the range extender circuit generates a range valid signal when a pulse at an output of the comparator exceeds a predetermined width.

50. The time to digital converter of claim 49 wherein the first and second counters each comprise a binary counter.

51. The time to digital converter of claim 49 wherein the predetermined width is determined by a delay element coupled between the output of the comparator and a flip flop.

52. The time to digital converter of claim 49 wherein the predetermined width is determined by a delay element coupled between the first clock signal and an input to the first counter.

53. The time to digital converter of claim 46 comprising a range extender circuit, the range extender circuit suppressing the coincidence signal until corresponding reference points of the first and second clock signals are within one half of one period of the second clock signal relative to one another.

54. The time to digital converter of claim 53 wherein the corresponding reference points comprise corresponding signal edges and the range extender circuit is configured to suppress the coincidence signal until no other edges of the first and second clock signals lie between the corresponding edges of the first and second clock signals.

55. The time to digital converter of claim 53 wherein:

the range extender circuit comprises a first counter connected to count reference points of the first signal, a second counter connected to count reference points of the second signal and a comparator connected to compare outputs of the first and second counters; and

,

the range extender circuit generates a range valid signal when a pulse at an output of the comparator exceeds a predetermined width.

56. The time to digital converter of claim 55 wherein the first and second counters each comprise a binary counter.

57. The time to digital converter of claim 55 wherein the predetermined width is determined by a delay element coupled between the output of the comparator and a flip flop.

58. The time to digital converter of claim 55 wherein the predetermined width is determined by a delay element coupled between the first clock signal and an input to the first counter.

59. The time to digital converter of claim 44 comprising an edge sampler wherein the START signal is generated by the edge sampler.

60. The time to digital controller of claim 44 comprising an edge sampler, the edge sampler generating the START signal and a STOP signal, the START signal connected to start the first oscillator and the stop signal connected to start the second oscillator.

61. The time to digital converter of claim 60 wherein the edge sampler is configured to generate the START signal upon a first edge of a test signal and to generate the STOP signal upon a second, subsequent, edge of the test signal.

62. The time to digital converter of claim 61 wherein the edge sample is configured to generate the START and STOP signals in a plurality of subsequent periods of the test signal.

63. The time to digital converter of claim 44 wherein at least one of the first and second oscillators comprises a plurality of digitally controllable delay elements.

64. The time to digital converter of claim 63 wherein, in each of the oscillators, the plurality of digitally controllable delay elements comprises a series of digitally controllable delay elements and a delay provided by an I^th one of the delay elements is controllably variable by an amount τ

_CDE(I) where τ

_CDE(I) for the delay elements in the series of digitally controllable delay elements are related to one another by τ

_CDE(I)=(1+ξ

)τ

_CDE(I-1) where ξ

is a number with 1<

(1+ξ

)<

2 and I is an index which identifies the delay elements in the series.

65. The time to digital converter of claim 63 wherein, in the at least one of the oscillators, the plurality of digitally controllable delay elements comprises a series of digitally controllable delay elements which provide delays τ

_CDE which are substantially equal to one another.

66. The time to digital converter of claim 63 comprising a state machine having outputs connected to control each of the plurality of digitally controllable delay elements.

67. The time to digital converter of claim 63 wherein the first and second oscillators comprise ring oscillators.

68. The time to digital converter of claim 63 wherein the controllable delay elements each comprise a gate having an input and output connected in a signal path and a variable load element connected to the output.

69. The time to digital converter of claim 68 wherein the variable load element comprises a tri-state device having an input connected to the output of the gate.

70. The time to digital converter of claim 69 wherein the tri-state device comprises a tri-NOT gate.

71. The time to digital converter of claim 68 wherein the load element comprises a capacitor connected in series between the output of the gate and a digital switch.

72. The time to digital converter of claim 71 wherein the capacitor comprises an NMOS gate capacitor having a gate electrode connected to the output of the gate.

73. The time to digital converter of claim 44 comprising an edge sampler connected to trigger the first and second oscillators upon detecting first and second reference points in a signal output from a circuit under test.

74. The time to digital converter of claim 73 wherein the circuit under test comprises a PLL.

75. The time to digital converter of claim 73 wherein the time to digital converter and the circuit under test are both on an integrated circuit and the time to digital converter comprises a data output for conveying off-chip timing data relating to the signal output from the circuit under test.

76. The time to digital converter of claim 75 wherein the data output comprises a serial data output.

77. A time to digital converter comprising:

means for generating first and second clock signals respectively having first and second periods;

means for varying at least one of the first and second periods to reduce a difference between the first and second periods from a first value T<sub>Δ

1</sub> to a second value T<sub>Δ

2</sub> where T<sub>Δ

2</sub><

T<sub>Δ

1</sub>;

means for operating the means for varying the at least one of the first and second periods when a reference point in the first clock signal has a known time relationship to a corresponding reference point on the second clock signal; and

,

means for counting features of the first clock signal.

78. The time to digital converter of claim 77 wherein the means for counting features of the first clock signal comprises means for counting the features of the first clock signal while the difference between the first and second periods has the first value T_Δ

1.

79. The time to digital converter of claim 78 wherein the means for counting features of the first clock signal comprises means for counting the features of the first clock signal while the difference between the first and second periods has the second value T_Δ

2.

80. The time to digital converter of claim 77 comprising means for estimating a difference in periods of the first and second clock signals.

81. The time to digital converter of claim 77 comprising means for adjusting a difference in periods of the first and second clock signals to have a value within a desired range.

82. The time to digital converter of claim 77 comprising means for suppressing operation of the means for varying at least one of the first and second periods until the first and second clock signals are within one period of the second clock signal relative to one another.

83. The time to digital converter of claim 77 comprising means for controlling the time to digital converter to repeatedly measure a period of a test signal.

84. The time to digital converter of claim 77 comprising means for switching the known time relationship between at least two values.

85. The time to digital converter of claim 77 comprising means for determining an internal jitter of the time to digital converter.

86. The time to digital converter of claim 77 comprising means for obtaining a corrected jitter measurement for a test signal based upon an internal jitter determined by the means for determining an internal jitter of the time to digital converter.

87. A method for time to digital conversion comprising providing first and second digital oscillators having a first state wherein a difference in periods of the first and second signals is T_Δ

1 and a second state wherein a difference in periods of the first and second signals is T<sub>Δ

2</sub> where T<sub>Δ

2</sub><

T<sub>Δ

1</sub>;

with the first and second digital oscillators in the first state, starting the first oscillator upon the occurrence of a first control signal and starting the second oscillator on the occurrence of a second control signal a time T_d later;

when reference points of the first and second signals occur within a predetermined time delay of one another switching the oscillators to the second state;

counting a number (N_C) of edges of the first clock signal which occur while the oscillators are in the first state;

counting a number (N_F) of edges of the first clock signal which occur while the oscillators are in the second state; and

,

stopping counting the number (N_F) when the reference points have a specified time relationship.

88. The method of claim 87 wherein the reference points are edges of the first and second signals and the specified time relationship is coincidence of the edges.

89. The method of claim 87 comprising acquiring a first set of the numbers N_F and N_C for T_d having a known value T_ref while the known time delay has a first value and a second set of the numbers N_F and N_C for T_d having a known value T_ref, a known multiple of T_ref, or a known fraction of T_ref, while the known time delay has a second value.

90. The method of claim 89 comprising averaging N_F and N_C for each of the first and second sets of measurements.

91. The method of claim 87 comprising generating the first control signal at the occurrence of a reference point in a test signal and generating the second control signal at the occurrence of a second reference point in the test signal.

92. The method of claim 91 wherein the first and second reference points in the test signal are separated by one period of the test signal.

93. The method of claim 91 wherein the first and second reference points in the test signal are edges of the test signal.

94. The method of claim 91 comprising repeating the method for a plurality of periods of the test signal to obtain a set of numbers N_C and N_F and subsequently deriving timing information relating to the test signal from the set of numbers N_C and N_F for the test signal while the known time delay has the first value.

95. The method of claim 91 comprising acquiring a first set of the numbers N_F and N_C for the test signal while the known time delay has a first value and a second set of the numbers N_F and N_C for the test signal while the known time delay has a second value.

96. The method of claim 95 comprising determining first and second measures of jitter of the test signal from each of the first and second sets of numbers.

97. The method of claim 96 comprising determining an internal jitter of a measurement system comprising the first and second oscillators based upon differences between the first and second measures of jitter.

98. The method of claim 97 wherein the first and second sets of numbers each comprise at least 500 pairs of numbers.

99. The method of claim 97 wherein the first and second sets of numbers each comprise at least 1000 pairs of numbers.

100. The method of claim 97 wherein the first value is larger than the second value and determining the internal jitter of a measurement system includes multiplication or division by a parameter a given by:

$\mathrm{\alpha <br><br>}=\frac{\stackrel{\_}{N_2}}{\stackrel{\_}{N_1}}$

where N_{2 is NF}+N_C for a pair of numbers in the second set of numbers and N₁ is N_F+N_C for a pair of numbers in the first set of numbers.

101. The method of claim 97 comprising obtaining a corrected measure of jitter of the test signal by performing one or more operations which include subtracting the internal jitter.

102. The method of claim 94 comprising obtaining a corrected measure of jitter of a test signal by performing one or more operations which include correcting for an internal jitter of a measurement system comprising the first and second oscillators.

103. The method of claim 94 wherein repeating the method for a plurality of cycles of the test signal to obtain a set of numbers N_C and N_F is performed on an integrated circuit chip and deriving a measure of jitter in the test signal from the set of numbers N_C and N_F is performed off-chip.

104. The method of claim 87 comprising suppressing switching the oscillators to the second state until corresponding features of the first and second clock signals are within one period of the second clock signal relative to one another.

105. The method of claim 87 comprising suppressing switching the oscillators to the second state until the first and second clock signals are within one half period of the second clock signal relative to one another.

106. The method of claim 87 comprising adjusting the first and second digital oscillators by:

starting the first and second oscillators at times separated by a known interval;

counting a number of features of at least one of the clock signals until reference points on the first and second clock signals have a known time relationship; and

,

if the number is not at least equal to a threshold value altering the period of at least one of the oscillators.

107. The method of claim 106 wherein adjusting the first and second oscillators comprises determining whether the first oscillator has a period longer than a period of the second oscillator and, if not, increasing the period of the first oscillator, decreasing the period of the second oscillator, or both increasing a period of the first oscillator and decreasing a period of the second oscillator.

108. The method of claim 106 wherein the first and second oscillators comprise a plurality of control inputs and adjusting the first and second oscillators comprises performing a search of combinations of the control inputs.

109. The method of claim 108 wherein the search is an exhaustive search.

110. The method of claim 106 wherein the first and second oscillators respectively comprise first and second pluralities of control inputs and adjusting the first and second oscillators comprises, if the period of the first oscillator is less than the period of the second oscillator performing a search of combinations of the first plurality of control inputs and, if the period of the second oscillator is less than the period of the first oscillator, performing a search of combinations of the second plurality of control inputs.

111. In apparatus for identifying a coincidence between first and second periodic signals, a range extender circuit comprising a first counter connected to count edges of the first signal, a second counter connected to count edges of the second signal, and a comparator connected to compare outputs of the first and second counters.

112. The range extender circuit of claim 111 comprising a circuit for generating a control signal when a pulse at an output of the comparator exceeds a predetermined width.

113. The range extender circuit of claim 112 wherein the first and second counters each comprise a k-bit counter.

114. The range extender circuit of claim 113 wherein the predetermined width is determined by a delay element coupled between the output of the comparator and a flip flop.

115. The range extender circuit of claim 113 wherein the predetermined width is determined by a delay element coupled between the first clock signal and an input to the first counter.