Memory array with read/write methods
First Claim
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1. A memory array comprising a plurality of independently addressable memory modules, wherein each memory module comprises:
- a plurality of memory cells arranged in rows and columns;
a plurality of sense amplifier latches, wherein each column of said memory cells is coupled to a corresponding one of said sense amplifier latches;
a plurality of decoder circuits coupled to said sense amplifier latches;
a plurality of data amplifiers coupled to said decoder circuits, wherein said data amplifiers amplify data signals read from said memory cells; and
a plurality of data lines coupling said data amplifiers to a set of bus lines, wherein the set of bus lines is commonly coupled to each of the plurality of memory modules, and wherein the set of bus lines transfers data signals to and from said memory modules, and wherein each of the memory modules further comprises a clock generating circuit configured to generate local control signals for the data amplifiers in response to a system clock signal.
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Abstract
Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.
563 Citations
2 Claims
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1. A memory array comprising a plurality of independently addressable memory modules, wherein each memory module comprises:
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a plurality of memory cells arranged in rows and columns;
a plurality of sense amplifier latches, wherein each column of said memory cells is coupled to a corresponding one of said sense amplifier latches;
a plurality of decoder circuits coupled to said sense amplifier latches;
a plurality of data amplifiers coupled to said decoder circuits, wherein said data amplifiers amplify data signals read from said memory cells; and
a plurality of data lines coupling said data amplifiers to a set of bus lines, wherein the set of bus lines is commonly coupled to each of the plurality of memory modules, and wherein the set of bus lines transfers data signals to and from said memory modules, and wherein each of the memory modules further comprises a clock generating circuit configured to generate local control signals for the data amplifiers in response to a system clock signal. - View Dependent Claims (2)
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Specification
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Current AssigneeInvensas Corporation
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Original AssigneeMonolithic System Technology
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InventorsLee, Winston, Hsu, Fu-Chieh, Leung, Wingyu
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Primary Examiner(s)Thai, Xuan M.
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Assistant Examiner(s)King, Justin
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Application NumberUS09/535,656Time in Patent Office1,552 DaysField of Search710/100, 710/307, 710/305, 365/189.04, 365/233, 365/203, 365/207, 365/208, 365/210, 365/230.01, 365/230.03, 365/206, 257/306, 714/759, 327/141, 711/103.151US Class Current710/100CPC Class CodesG06F 13/40 Bus structure for computer ...G06F 13/4072 Drivers or receivers G06F13...G06F 13/4077 Precharging or dischargingH04L 25/026 Arrangements for coupling t...H04L 25/028 Arrangements specific to th...H04L 25/0292 Arrangements specific to th...Y02D 10/00 Energy efficient computing,...
