Multi-board connection system for use in electronic design automation

• US 6,754,763 B2
• Filed: 03/06/2002
• Issued: 06/22/2004
• Est. Priority Date: 07/30/2001
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Axis Systems Incorporated (Cadence Systems, Inc.)
• Inventors: Lin, Sharon Sheau-Pyng
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US10/092,839
• Publication Number:
  US 20030144828A1
• Time in Patent Office: 839 Days
• Field of Search: 710/100, 710/300, 710/305, 710/306, 710/313, 710/317, 361/748, 361/760, 361/783, 361/785, 361/792, 361/803, 712/33, 370/254, 370/257, 709/253, 340/825
• US Class Current: 710/317
• CPC Class Codes: G06F 15/7864 on more than one IC chip
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A high fan-out hub array system and method is provided. The system includes at least one hub that contains user logic that receive signals from various chips and boards, and which quickly turnarounds another signal (based on the logic) out to the desired chips and boards. In a CLKGEN implementation, a global clock is generated in the hub and distributed in a high fan-out manner to all the FPGA logic chips in the system. For a bus resolution application, a hub contains bus resolution logic to resolve bus access requests. It resolves the various requests and delivers the result to all the relevant chips and boards. In a STOPWHEN application, when a STOPWHEN condition has been met, the system delivers a pause signal to all the chips and boards via the high fan-out hubs.

Claims

1. A multi-board interconnect system in a motherboard for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:

a local bus interconnect separated from the motherboard via the motherboard connector and the local bus interconnect, and including a plurality of first hardware elements and a first logic bus coupling the plurality of first hardware elements and the first logic bus coupled to the local bus interconnect;

a second board directly coupled to the first board via the local bus interconnect and including a plurality of second hardware elements and a second logic bus coupling the plurality of second hardware elements and the second logic bus coupled to the local bus interconnect, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of second hardware elements in the second board via the local bus; and

a hub coupling the plurality of first hardware elements and plurality of second hardware elements.

2. The system of claim 1, wherein the hub can couple the plurality of first and second hardware elements in two hops.

3. the system of claim 1, wherein the plurality of first hardware elements is a first logic device and a first memory device.

4. The system of claim 3, wherein the plurality of second hardware elements is a second logic device and a second memory device.

5. The system of claim 4, wherein the first board and the second board are coupled together through a first inter-board connector which is separated from the motherboard connector and couples the first logic device and the second logic device.

6. The system of claim 5, further comprising:

a local bus controller coupled to the system bus and the local bus interconnect on the first board for controlling data transfer between the system bus and the local bus.

7. The system of claim 1, wherein the first board has a first solder side and a first component side, and the second board has a second solder side and a second component side, and the local bus interconnect couples the first component side and the second solder side.

8. The system of claim 5, wherein the first board has a first solder side and a first component side, and the second board has a second solder side and a second component side, and the first inter-board connector couples the first component side to the second solder side.

9. The system of claim 5, further comprising:

a third board directly coupled to the motherboard and the local bus interconnect, the third board having component side and a third solder side, the local bus interconnect coupling the third board and the second board; and

a second inter-board connector which is separated from the motherboard connector and connects the second board and the third board, wherein the second inter-board connector coupled couples the second component side to the third solder side.

10. The system of claim 6, further comprising:

a logic bus controller coupled to the local bus interconnect and the first logic bus on the first board, and coupled to the local bus interconnect and the second logic bus on the second board, for controlling data transfer among the local bus interconnect, the first logic bus, and the second logic bus.

11. The system of claim 1, wherein the plurality of first hardware elements in the first board and the plurality of second hardware elements in the second board form an array of horizontal rows and vertical columns, where a hub is provided for each vertical column coupling the hardware elements in the vertical column and the hubs are coupled together.

12. A multi-board connection system in a motherboard for an electronic system, the motherboard containing a motherboard connector and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:

an inter-board connection separated from the motherboard connector;

a first board directly coupled to the motherboard via the motherboard connector and including a plurality of first hardware elements and a first logic bus coupling the plurality of first hardware elements;

a second board directly coupled to the first board via the inter-board connection and including a plurality of second hardware elements and a second logic bus coupling the plurality of second hardware elements, wherein at least one of the plurality of first hardware elements in the first board is coupled to at least one of the plurality of second hardware elements in the second board via the inter-board connection;

a third board directly coupled to the second board via the inter-board connection and directly coupled to the motherboard via the motherboard connector, and the third board including a plurality of third hardware elements, wherein at least one of the plurality of second hardware elements in the second board is coupled to at least one of the plurality of third hardware elements in the third board via the inter-board connection; and

a hub coupling the plurality of first hardware elements, second hardware elements, and third hardware elements together so that any hardware element can communicate with any other hardware element in two hops.

13. The system of claim 12, wherein the plurality of first hardware elements is a first logic device and a first memory device.

14. The system of claim 13, wherein the plurality of second hardware elements is a second logic device and a second memory device.

15. The system of claim 14, wherein the first board and the second board are coupled together through a first inter-board connector which is separated from the motherboard connector and couples the first logic device and the second logic device.

16. The system of claim 15, further comprising:

a local bus in the first board and the second board coupled to the system bus; and

a local bus controller coupled to the system bus and the local bus on the first board for controlling data transfer between the system bus and the local bus.

17. The system of claim 16, further comprising:

a logic bus controller coupled to the local bus and the first logic bus on the first board, and coupled to the local bus and the second logic bus on the second board, for controlling data transfer among the local bus, the first logic bus, and the second logic bus.

18. The system of claim 12, wherein the first board has a first solder side and a first component side, and the second board has a second solder side and a second component side, and the inter-board connection couples the first component side and the second solder side.

19. The system of claim 12, wherein the plurality of first hardware elements in the first board are arranged in a two-dimensional matrix of rows and columns.

20. The system of claim 19, wherein the plurality of second hardware elements in the second board are arranged in a two-dimensional matrix of rows and columns.

21. The system of claim 20, wherein a hub is provided for each column coupling the plurality of first hardware elements and the plurality of second hardware elements in the column together and the hubs are coupled together.

22. The system of claim 19, wherein the first board is expandable to include additional rows of first hardware elements.

23. A multi-board connection system in a motherboard for an electronic system, the motherboard containing a motherboard connection and a host computer system, the host computer including a processor, a main memory, a processor bus system coupled to the processor and main memory, and a system bus coupled to the processor bus, comprising:

an interboard connection separated from the motherboard connector;

a first board directly coupled to the motherboard via the motherboard connector and including at least one row of a plurality of first logic devices and a first logic bus coupling the plurality of first logic devices;

a second board directly coupled to the first board via the inter-board connection and including at least one row of a plurality of second logic device and a second logic bus coupling the plurality of second logic devices, wherein the first board and second board collectively form an array of a plurality of rows and columns of logic device; and

a hub provided for each column coupling the logic devices in that column, where each of the hubs in each column is coupled together.

24. The system of claim 23, wherein any of the plurality of first and second logic device can communicate with each other through the hub in 2 hops.

25. The system of claim 23, wherein the hub contains user logic to process incoming data from the plurality of first logic devices and second logic devices.