Flash memory controller with updateable microcode

• US 6,754,765 B1
• Filed: 05/14/2001
• Issued: 06/22/2004
• Est. Priority Date: 05/14/2001
• Status: Active Grant

• Current Assignee: Integrated Memory Logic Limited (Maxlinear Incorporated)
• Original Assignee: Integrated Memory Logic Limited (Maxlinear Incorporated)
• Inventors: Chang, Chao-I, Zhang, Ji Yun
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): BAKER, PAUL A
• Application Number:
  US09/855,919
• Time in Patent Office: 1,135 Days
• Field of Search: 711/103, 711/157, 711/164
• US Class Current: 711/103
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57

Abstract

A flash memory controller with a volatile program and data memory is disclosed. The controller loads microcode and data into the program and data memory from a flash memory array upon powerup of the controller. If an error occurs during the download or the microcode does not exist in the flash memory array, then the controller loads microcode and data into the program and data memory from the host computer. In some embodiments of the invention, an initial code is downloaded to the controller so that an evaluation of the configuration of the controller and the flash memory can be communicated to a host computer. The host computer then downloads for storage into the flash memory a tailored microcode and restarts the controller so that the tailored microcode is loaded from the flash memory and executed. In some embodiments, a protection circuit is provided to protect the microcode from accidentally being erased from the flash memory. Additionally, in some embodiments, an interleaved data structure is utilized to minimize wait times during read and write operations to the flash memory.

Claims

1. A flash memory controller, comprising:

a host interface that can couple with a host computer;

a flash memory interface that can couple with a flash memory;

a volatile memory area for storing microcode and data; and

a microcontroller coupled to execute microcode stored in the volatile memory area; and

wherein the microcode can be loaded into the volatile memory area through the flash memory interface, and

wherein tailored microcode and data can be loaded into the flash memory from the host computer if the microcode and data are not correctly loaded into the volatile memory area from the flash memory.

2. The controller of claim 1, wherein new microcode is loaded into the flash memory from the host computer if a portion of the microcode is blank in the flash memory.

3. The controller of claim 1, wherein data is loaded into the volatile memory area through the flash memory interface and wherein data can be loaded into the flash memory from the host computer before the data is loaded into the volatile memory area from the flash memory.

4. The controller of claim 3, wherein data and microcode are both loaded into the flash memory from the flash controller together.

5. The controller of claim 4, wherein new microcode and data are loaded into the flash memory from the host computer if a portion of either the microcode or the data is blank in the flash memory.

6. The controller of claim 3, wherein the data includes card information structure (CIS) data.

7. The controller of claim 3, wherein the data includes a memory mapping table.

8. The controller of claim 7, wherein the memory mapping table includes a mapping of logical addresses to physical addresses that maps out bad blocks in the flash memory.

9. The controller of claim 3, wherein the data includes a file allocation table.

10. The controller of claim 1, further including an error correction circuit for detecting errors in microcode loaded from the flash memory.

11. The controller of claim 10, wherein new microcode is loaded into the flash memory if the error correction circuit detects an error in the microcode loaded from the flash memory.

12. The controller of claim 3, further including an error correction circuit for detecting errors in microcode and data loaded from the flash memory.

13. The controller of claim 12, wherein new microcode and data are loaded into the flash memory if the error correction circuit detects an error in the microcode loaded from the flash memory.

14. The controller of claim 1, further including a protection circuit that prevents accidental erasure of a portion of flash memory that stores the microcode.

15. The controller of claim 14, wherein the protection circuit compares an erase address with a range of addresses where the microcode is stored and outputs an error message if a password loaded into a password register does not match a stored password.

16. The controller of claim 1, further including a memory management system having an interleaved data structure.

17. The controller of claim 16, wherein the interleaved data structure is a two-chip interleave where sectors of data are alternately stored between a first block in a first chip and a second block in a second chip.

18. The controller of claim 16, wherein the interleaved data structure is multi-chip interleave where data is stored in a round-robin fashion between a block in each of a plurality of chips.

19. A method of powering up a flash memory controller, comprising:

indicating a PC Card busy;

executing a firmware shadowing algorithm to load microcode from a flash memory bank into a volatile memory area;

indicating a state of the loading from the flash memory bank, wherein the state indicates either a successful loading or a not successful loading from the flash memory bank; and

,

if the state is successful, starting a microprocessor to execute the microcode and entering a normal mode of operation;

or,

if the state is not successful, executing a download algorithm to receive microcode from a host computer interface.

20. The method of claim 19, further including

executing the firmware shadowing algorithm to load data from the flash memory bank into the volatile memory area, and

wherein indicating the state includes indicating the state of loading of the data to the volatile memory area.

21. The method of claim 20, wherein the data includes card information structure data.

22. The method of claim 20, wherein the data includes memory mapping data.

23. The method of claim 22, wherein the memory mapping data maps logical addresses to physical addresses such that bad blocks of the flash memory bank are mapped out.

24. The method of claim 20, wherein the data includes file attribute data.

25. The method of claim 20, wherein executing a download algorithm comprises:

indicating and signaling a PC ready;

receiving an initial microcode from the host computer interface;

executing the initial microcode;

receiving a tailored microcode from the host computer interface and storing the tailored microcode in the flash memory bank; and

restarting the power up algorithm to load the tailored microcode from the flash memory bank into the volatile memory area.

26. The method of claim 25, wherein executing the initial microcode includes

analyzing the flash memory bank;

and

sending information regarding the flash memory bank and the controller to the host computer interface.

27. The method of claim 25, wherein a host computer coupled to the host computer interface constructs the tailored microcode and data to be transmitted to the host computer interface.

28. The method of claim 19, wherein receiving the tailored microcode and storing the tailored microcode comprises:

writing a password into a password register;

erasing blocks of the flash memory bank used for storing microcode;

transferring the tailored microcode from volatile memory area into the flash memory bank.

29. A flash memory controller, comprising:

means for loading microcode and data from the flash memory into volatile memory of the controller;

means for determining whether or not microcode and data were correctly loaded into the volatile memory;

means for receiving tailored microcode and data from a host computer if the microcode and data was not correctly loaded into the volatile memory from the flash memory.

30. The controller of claim 29, wherein the means for loading includes

means for receiving and executing initial microcode; and

means for transferring information to the host computer.

31. The controller of claim 29, wherein the means for determining includes

means for determining if there is an error in the microcode and data loaded from the flash memory to the volatile memory;

means for determining if a portion of the microcode or data in the flash memory is blank.

32. The controller of claim 29, wherein the means for receiving includes

means for transferring the microcode and data as data from the host computer into the flash memory.

33. The controller of claim 29, further including

means for interleaved reading and writing data into the flash memory.

34. The controller of claim 29, further including

means of protecting a portion of the flash memory from accidental overwrite, the portion of the flash memory being the portion utilized to store microcode and data utilized by the microcode.

35. A flash memory controller, comprising:

a host interface that can couple with a host computer;

a flash memory interface that can couple with a flash memory;

a volatile memory area for storing microcode and data; and

a microcontroller coupled to execute microcode stored in the volatile memory area; and

wherein the microcode and data can be loaded into the volatile memory area through the flash memory interface, and

wherein tailored microcode and data can be loaded into the flash memory from the host computer before the microcode is loaded into the volatile memory area from the flash memory.

36. The controller of claim 35, wherein the microcontroller executes an initial microcode received from the host computer to receive the tailored microcode from the host computer.

37. The controller of claim 36, wherein information is provided to the host computer by the controller when the initial microcode is executed.

38. The controller of claim 37, wherein the tailored microcode and data and written into the flash memory by the controller when the initial microcode is executed.