Methods and circuits for securing encached information

• US 6,754,784 B1
• Filed: 06/30/2000
• Issued: 06/22/2004
• Est. Priority Date: 02/01/2000
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: North, Gregory Allen, Kircher, Brian Christopher, Perry, Matthew Richard
• Primary Examiner(s): Nguyen, Hiep T.
• Assistant Examiner(s): DINH, NGOC V
• Application Number:
  US09/608,055
• Time in Patent Office: 1,453 Days
• Field of Search: 711/133, 711/145, 711/147, 711/138, 711/163, 713/193
• US Class Current: 711/145
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 21/572 Secure firmware programming, e.g. of basic input output system [BIOS]
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 2211/1097 Boot, Start, Initialise, Power

Abstract

A system 100 including a central processing unit 101 operates in response to a set of instructions for processing information. A port 134 provides access to selected circuitry forming a part of the system by an external device. A set of non-volatile programmable security elements 136 selectively enable and disable the operation of the interface to provide a private environment for processing the information.

Claims

1. A method of preventing access and observation of encached information comprising the steps of:

generating private information to be encached;

storing the private information in memory;

updating a translation look aside buffer with descriptors to locations in memory containing the private information;

forcing a cache miss to a selected location in cache to be loaded with a selected portion of the private information;

retrieving the selected portion of the private information from memory using a corresponding descriptor from the translation look aside buffer;

loading the retrieved portion of the private information into the selected location in cache; and

locking the selected portion of the private information in the selected location in cache.

2. The method of claim 1 and further comprising the step of locking the descriptor corresponding to the selected portion of the private information in the translation look aside buffer.

3. The method of claim 1 wherein said selected location in cache is associated with a replacement counter base and said step of locking comprises the substep of resetting the replacement counter base to a value higher than the replacement counter base associated with the selected location in cache.

4. The method of claim 1 wherein said step of updating the translation look aside buffer comprises the substeps of:

setting up a translation table including entries for generating the descriptors to memory locations storing the private information;

updating a replacement counter to point to a current translation look aside buffer entry to be filled;

forcing a miss to the current translation look aside buffer entry;

performing a table walk through the translation table to generate a descriptor associated with private information in memory; and

loading the descriptor obtained from the table walk in the current translation look aside buffer entry.

5. The method of claim 1 wherein said step of loading the retrieved portion of the private information into the selected location in cache comprises the step of loading a cache line in instruction cache.

6. The method of claim 1 wherein said step of loading the selected portion of the private information in cache comprises the step of loading a cache line in data cache.

7. The method of claim 1 wherein said step of updating the translation look aside buffer comprises a step of setting up a translation table comprises the step of setting up an emulated translation table.

8. A processing system comprising:

a memory for storing private information to be secured;

cache memory having a target location for encacheing said private information;

a translation look aside buffer having a location for storing a descriptor for accessing said private information from said memory; and

control circuitry operable to;

force a miss to the target location in said cache;

retrieve the private information from said memory using said descriptor in said translation look aside buffer;

load the retrieved private information into the target location in said cache; and

lock said private information in the target location in said cache.

9. The processing system of claim 8 wherein said control circuitry is further operable to lock said descriptor in said translation look aside buffer.

10. The processing system of claim 8 wherein said control circuitry comprises a counter pointing to the target location and is operable to lock said private information into the target location in said cache by resetting a base value loaded in said counter.

11. The processing system of claim 8 wherein said control circuitry and said translation look aside buffer comprise a portion of a microprocessor.

12. The processing system of claim 11 wherein said cache comprises a portion of a microprocessor.

13. The processing system of claim 12 wherein said microprocessor comprises a portion of a system-on-a-chip.

14. The processing system of claim 8 wherein said cache comprises an instruction cache.

15. The processing system of claim 8 wherein said cache comprises a data cache.