Switched multi-channel network interfaces and real-time streaming backup

• US 6,754,785 B2
• Filed: 11/30/2001
• Issued: 06/22/2004
• Est. Priority Date: 12/01/2000
• Status: Expired due to Fees

• Current Assignee: James R. Hsia, Yan Chiew Chow
• Original Assignee: James R. Hsia, Yan Chiew Chow
• Inventors: Hsia, James R., Chow, Yan Chiew
• Primary Examiner(s): Sparks, Donald
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US10/007,415
• Publication Number:
  US 20020069334A1
• Time in Patent Office: 935 Days
• Field of Search: 707/2, 707/10, 707/202, 707/204, 707/205, 709/201, 709/213, 709/217, 709/220, 709/223, 710/22, 711/104, 711/112, 711/114, 711/147, 711/156, 711/162, 711/170, 711/173, 714/6, 714/47, 714/52, 714/758, 714/759, 714/769, 714/770, 714/773, 714/777
• US Class Current: 711/147
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0873 Mapping of cache memory to specific storage devices or parts thereof
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/262 configured as RAID
• CPC Class Codes: G06F 2212/263 Network storage, e.g. SAN or NAS
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: Y10S 707/99932 Access augmentation or optimizing

Abstract

A memory system (100) and method of operating the same for storing, manipulating, processing, and transferring data in a data network (120). Generally, the memory system (100) includes one or more memory matrixes (110) for storing data therein, a non-volatile storage module (NVSM 130), and a management module (125) coupling the network (120) to the memory matrix and to the NVSM. The management module (125) is configured to enable the network (120) to access the memory matrix (110) during normal operation to provide a primary memory, and to stream data from the primary memory matrix to secondary memory matrixes to the NVSM (130) to provide staged backup memories. Optionally, the memory system (100) further includes an off-line storage module (OLSM 135), and an uninteruptible power supply (UPS 140). In one embodiment, the management module (125) is linked to the network (110), the memory matrix (110), the NVSM (120), the UPS (140) and the OLSM (135) through multiple switched network interfaces (360) with link failover and fail back capability to provide high availability.

Claims

1. A memory system for use in a data network, the memory system comprising:

a memory matrix unit having a memory matrix capable of storing data therein;

a non-volatile storage unit capable of storing data therein;

a management unit configured to couple the data network to the memory matrix unit via a primary network interface and to the non-volatile storage unit via a secondary network interface, the management unit further configured to enable the data network to access the memory matrix during normal operation to provide a primary memory, and to stream data from the data network to the non-volatile storage unit to provide a backup memory;

wherein the memory matrix comprises;

a plurality of Random Access Memory (RAM) devices each capable of storing data therein, the memory devices arranged in a plurality of banks each having a predetermined number of memory devices;

a memory controller coupled to each of the banks and capable of accessing the memory devices; and

a cache coupled to the memory controller, the cache having stored therein one or more copies of a Data Allocation Table (DAT) adapted to describe data stored in the memory devices; and

wherein the management unit further comprises;

a primary processor coupled to the memory controller of a memory matrix;

a read-only memory (ROM) device coupled to the Primary processor, the ROM device having stored therein an initial boot sequence to boot the management unit;

a memory device coupled to the primary processor to provide a buffer memory to the primary processor;

a switch coupled to the primary processor through a network interface controller and through the network to a plurality of data Processing systems;

one or more secondary processors coupled to the memory controller;

a second ROM device coupled to each secondary processor, the second ROM device having stored therein an initial boot sequence to boot the secondary processor;

a second memory device coupled to each secondary processor to provide a buffer memory to the secondary processor;

a wireless network unit coupled to the primary processor through a bus; and

a security processor coupled to the primary processor through a bus.

2. The memory system of claim 1, further including a secondary memory coupled to the management unit via the secondary network interface, and wherein the management unit is further configured to:

detect a non-operating condition of the primary memory;

reconfigure the secondary network interface to enable the data network to access a secondary memory if the secondary memory is available; and

reconfigure the secondary network interface to enable the data network to access the backup memory in the non-volatile storage unit if the secondary memory is unavailable,

whereby failover to the backup memory is transparent to a user of the data processing system.

3. The memory system of claim 1, wherein at least one of the network interfaces comprises an interface standard selected from a group consisting of:

gigabit Ethernet;

ten gigabit Ethernet;

Fibre Channel-Arbitrated Loop (FC-AL);

Firewire;

Small Computer System Interface (SCSI);

Advanced Technology Attachment (ATA);

InfiniBand;

HyperTransport;

PCI-X;

Direct Access File System (DAFS);

IEEE 803.11; and

Wireless Application Protocol (WAP).

4. The memory system of claim 1, wherein the primary network interface comprises a plurality of network interfaces connected in parallel, the network interfaces configured to provide higher data transfer rates in normal operation and to provide access to the memory matrix at a reduced data transfer rate should one of the network interfaces fail.

5. The memory system of claim 1, wherein the non-volatile storage unit comprises one or more disk drives.

6. The memory system of claim 3, wherein the disk drive is adapted to create a snapshot backup of data in the memory matrix.

7. The memory system of claim 6, wherein management unit is configured to automatically create the snapshot backup at predetermined intervals.

8. The memory system of claim 5, wherein the disk drive is adapted to continuously backup data in the memory matrix.

9. A method of configuring a memory system for a data network, comprising the steps of:

providing a plurality of Random Access Memory (RAM) devices each capable of storing data therein, the memory devices arranged in a plurality of banks each having a predetermined number of memory devices;

coupling a memory controller coupled to each of the banks to form a memory matrix, the memory controller capable of accessing the memory devices;

coupling a cache to the memory controller, the cache having stored therein one or more copies of a Data Allocation Table (DAT) adapted to describe data stored in the memory devices;

providing a management unit by;

coupling a primary processor to the memory controller of a memory matrix;

coupling a read-only memory (ROM) device to the Primary processor, the ROM device having stored therein an initial boot sequence to boot the management unit;

coupling a memory device to the primary processor to provide a buffer memory to the primary processor;

coupling a switch to the Primary processor through a network interface controller and through the network to a plurality of data processing systems;

coupling one or more secondary processors to the memory controller;

coupling a second ROM device to each secondary processor, the second ROM device having stored therein an initial boot sequence to boot the secondary processor;

coupling a second memory device to each secondary processor to provide a buffer memory to the secondary processor;

coupling a wireless network unit to the Primary processor through a bus; and

coupling a security processor to the primary processor through a bus;

coupling the memory matrix to the data network through the management unit to enable the network to access the memory matrix as primary memory; and

coupling a non-volatile storage unit to the data network through the management unit to enable the data network to access the non-volatile storage unit as backup memory.

10. The method of claim 9 further comprising the steps of:

detecting a non-operating condition of the primary memory; and

reconfiguring the memory system to enable the data network to access the backup memory.

11. The method of claim 10, wherein the memory system further comprises an additional memory matrix configured to mirror the memory matrix of the primary memory, and wherein prior to reconfiguring the memory system to enable the data network to access the backup memory the method further comprises the steps of:

detecting availability of the additional memory matrix; and

reconfiguring the memory system to enable the data network to access the additional memory matrix as an instant backup of the primary memory.

12. The method of claim 10, further comprising the steps of:

detecting a non-operating condition of the backup memory; and

reconfiguring a memory system to enable the data network to access the non-volatile storage unit if the backup memory is unavailable.

13. The method of claim 9, wherein the step of coupling the memory matrix to the data network, and the step of coupling the non-volatile storage unit to the data network, comprise the step of using a bus interface standard selected from a group consisting of:

gigabit Ethernet;

ten gigabit Ethernet;

Fibre Channel-Arbitrated Loop (FC-AL);

Firewire;

Small Computer System Interface (SCSI);

Advanced Technology Attachment (ATA);

InfiniBand;

HyperTransport;

PCI-X;

Direct Access File System (DAFS);

IEEE 803.11; and

Wireless Application Protocol (WAP).

14. The method of claim 9, wherein the memory matrix comprises:

a plurality of Random Access Memory (RAM) devices each capable of storing data therein, the memory devices arranged in a plurality of banks each having a predetermined number of memory devices;

a memory controller coupled to each of the banks and capable of accessing the memory devices; and

a cache coupled to the memory controller, the cache having stored therein a Data Allocation Table (DAT) adapted to describe data stored in the memory devices.