System and method for terminating lock-step sequences in a multiprocessor system

• US 6,754,787 B2
• Filed: 11/22/2002
• Issued: 06/22/2004
• Est. Priority Date: 10/03/1997
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Miller, Robert J., McDonald, Edward A.
• Primary Examiner(s): THAI, TUAN V
• Application Number:
  US10/302,372
• Publication Number:
  US 20030070050A1
• Time in Patent Office: 578 Days
• Field of Search: 711/118, 711/100, 711/152, 711/154, 711/163, 711/167, 711/168
• US Class Current: 711/152
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.

Claims

1. For use in a processing system containing a plurality of processors coupled to a main memory by a first common bus, a control circuit for breaking a lock-step sequence of memory requests received from said processors, said control circuit comprising:

a memory request generator coupled to said first common bus for generating a first additional memory request independent of the memory requests of the lock-step sequence, the first additional memory request having higher service priority than the memory requests of the lock-step sequence to disturb a timing of the lock-step sequence of the memory requests;

wherein a duration of the first additional memory request is generated pseudo-randomly.

2. The control circuit set forth in claim 1 wherein the first additional memory request is generated pseudo-randomly.

3. The control circuit set forth in claim 1 wherein said processing system further comprises a plurality of I/O devices coupled to said main memory by a second common bus and said memory request generator is adapted to be coupled to said second common bus and further generates a second additional memory request on said second common bus operable to terminate a second lock-step sequence of memory requests received from said I/O devices, the second additional memory request having a higher service priority than the memory requests of the second lock-step sequence of the I/O devices on the second common bus.

4. The control circuit set forth in claim 3 wherein the second additional memory request on said second common bus is generated pseudo-randomly.

5. The control circuit set forth in claim 3 wherein a duration of the second additional memory request on said second common bus is generated pseudo-randomly.

6. The control circuit set forth in claim 3 wherein the first additional memory request on said first common bus and the second additional memory request on said second common bus are generated simultaneously.

7. The control circuit set forth in claim 3 wherein the first additional memory request on said first common bus and the second additional memory request on said second common bus are generated at different times.

8. The control circuit set forth in claim 1, wherein the first additional memory request is generated independent of whether the lock-step sequence of memory requests exists.

9. A processing system comprising:

A plurality of processors;

a main memory;

a memory control device coupled to said plurality of processors by a first common bus and to said main memory to receive memory request from said plurality of processors and to transfer data between said plurality of processors and said main memory; and

a control circuit to break a lock-step sequence of memory requests received from said processors, said control circuit comprising a memory request generator coupled to said first common bus for generating a first additional memory request independent of the memory requests of the lock-step sequence, the first additional memory request having a higher service priority than the memory requests of the lock-step sequence to perturb a timing of the lock-step sequence memory requests;

wherein a duration of the first additional memory request is generated pseudo-randomly.

10. The processing system set forth in claim 9 wherein the first additional memory request is generated pseudo-randomly.

11. The processing system set forth in claim 9 further comprising a plurality of I/O devices coupled to said memory control device by a second common bus, wherein said memory request generator is coupled to said second common bus and further generates a second additional memory request on said second common bus operable to terminate a second lock-step sequence of memory requests received from said I/O devices.

12. The processing system set forth in claim 11 wherein the second additional memory request on said second common bus is generated pseudo-randomly.

13. The processing system set forth in claim 11 wherein a duration of the second additional memory request on said second common bus is generated pseudo-randomly.

14. The processing system set forth in claim 11 wherein the first additional memory request on said first common bus and the second additional memory request on said second common bus are generated simultaneously.

15. The processing system set forth in claim 11 wherein the first additional memory request on said first common bus and the second additional memory request on said second common bus are generated at different times.

16. The processing system set forth in claim 9, wherein the first additional memory request is generated independent of whether the lock-step sequence of memory requests exists.

17. In a processing system containing a plurality of processors coupled to a main memory by a first common bus, a method for perturbing a lock-step sequence of memory requests received from the processors, the method comprising:

generating a first additional memory request independent of the memory requests of the lock-step sequence on the first common bus, the first additional memory request having a higher service priority than the memory requests of the lock-step sequence to perturb a timing of the lock-step sequence of memory requests;

wherein a duration of the first additional memory request is generated pseudo-randomly.

18. The method set forth in claim 17 wherein the first additional memory request is generated pseudo-randomly.

19. The method set forth in claim 17 wherein the processing system further comprises a plurality of I/O devices coupled to the main memory by a second common bus, the method further comprises:

generating a second additional memory request on the second common bus, the second additional memory request on the second bus operable to terminate a second lock-step sequence of memory requests received from the I/O devices, and the second additional memory request having a higher service priority than the memory requests of the second lock-step sequence.

20. The method set forth in claim 17, wherein the first additional memory request is generated independent of whether the lock-step sequence of memory requests exists.