Algorithm for non-volatile memory updates
First Claim
1. A computer, comprising:
- a processor; and
a non-volatile memory, the processor being coupled to the non-volatile memory by a system bus, wherein the non-volatile memory includes a FLASH memory and the non-volatile memory further including;
a processor abstraction layer, and a system abstraction layer.
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Accused Products
Abstract
A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e.g. non-volatile ROM.
The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine. The system abstraction layer update procedure is used to call a specific non-volatile memory implementation routine.
73 Citations
43 Claims
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1. A computer, comprising:
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a processor; and
a non-volatile memory, the processor being coupled to the non-volatile memory by a system bus, wherein the non-volatile memory includes a FLASH memory and the non-volatile memory further including;
a processor abstraction layer, and a system abstraction layer. - View Dependent Claims (2, 3, 4, 5)
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6. A computer, comprising:
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a processor; and
a non-volatile memory, the processor being coupled to the non-volatile memory by a system bus, and the non-volatile memory further including;
a processor abstraction layer, wherein the processor abstraction layer includes multiple binary code blocks which provide a standard firmware interface to abstract processor implementation specific features of the processor; and
a system abstraction layer. - View Dependent Claims (7, 8, 9, 10)
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11. A computer, comprising:
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a processor; and
a non-volatile memory, the processor being coupled to the non-volatile memory by a system bus, and the non-volatile memory further including;
a processor abstraction layer, wherein the processor abstraction layer includes at least one binary code block comprising an enhancement to the processor; and
a system abstraction layer. - View Dependent Claims (12, 13, 14)
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15. A computer, comprising:
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a processor; and
a non-volatile memory, the processor being coupled to the non-volatile memory by a system bus, and the non-volatile memory further including;
a processor abstraction layer, and a system abstraction layer, wherein the system abstraction layer includes a procedure interface which imposes a unique header onto multiple binary blocks held in the processor abstraction layer for the non-volatile memory. - View Dependent Claims (16, 17)
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18. A computer, comprising:
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a processor; and
a non-volatile memory, the processor being coupled to the non-volatile memory by a system bus, and the non-volatile memory further including;
a processor abstraction layer, and a system abstraction layer, wherein the computer is a reliable available and serviceable computer. - View Dependent Claims (19, 20, 21)
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22. A method for an update to a non-volatile memory in an electronic system, comprising:
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starting in a firmware of the electronic system and marking a new input binary to be updated in the non-volatile memory;
starting an initialization mode in which a single processor (BSP) is selected for managing the operation of the update;
releasing a protected binary block in the non-volatile memory to be a normal block for programming;
communicating between the single processor and a system abstraction layer (SAL) procedure interface for calling an appropriate authentication routine to validate the new input binary that is executing in the initialization mode; and
providing the new input binary access to the non-volatile memory and copying the new input binary into the non-volatile memory to update the non-volatile memory if the new input binary is authenticated. - View Dependent Claims (23, 24, 25)
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26. A method for a run-time update of a non-volatile memory of an electronic system, comprising:
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exposing a system abstraction layer (SAL) update procedure to a caller program of an update utility for updating the non-volatile memory with a new input binary;
selecting a lead processor, in coordination with an operating system of the electronic system, to perform the run-time update using the SAL update procedure;
using the SAL update procedure to call an appropriate authentication routine to validate the new input binary; and
using the SAL update procedure to call a specific non-volatile memory implementation routine. - View Dependent Claims (27, 28, 29, 30, 31, 32)
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33. A method for authenticating a new input binary to a non-volatile memory of an electronic system, comprising:
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using a system abstraction layer procedure interface from the non-volatile memory to impose a unique header onto binary blocks in the non volatile memory;
exposing the system abstraction layer procedure interface to a caller program in a non-volatile memory update utility; and
using the system abstraction layer procedure interface to check the validity of the new input binary by calling an appropriate authentication routine from the non-volatile memory. - View Dependent Claims (34, 35, 36)
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37. A computer readable medium having computer-executable instructions, which when executed by a machine, cause the machine to perform operations comprising:
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invoking a system abstraction layer update procedure from a non-volatile memory to implement a new input binary into the non-volatile memory;
selecting a lead processor, in coordination with an operating system of an electronic system, to perform a run-time update using the system abstraction layer update procedure;
using the system abstraction layer update procedure to call an appropriate authentication routine; and
using the system abstraction layer update procedure to call a specific non-volatile memory implementation routine. - View Dependent Claims (38, 39)
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40. A method of communicating between a firmware update utility and a non-volatile memory, comprising:
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using a system abstraction layer procedure interface from the non-volatile memory for imposing a unique header onto multiple binary blocks in the non volatile memory;
exposing the system abstraction layer procedure interface to the firmware update utility; and
using the system abstraction layer procedure interface to check the validity of a new input binary by calling an appropriate authentication routine from the non-volatile memory. - View Dependent Claims (41, 42, 43)
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Specification