Over-clocking detection system utilizing a reference signal and thereafter preventing over-clocking by reducing clock rate

• US 6,754,840 B2
• Filed: 12/10/2002
• Issued: 06/22/2004
• Est. Priority Date: 09/29/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Poisner, David I.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): SURYAWANSHI, SURESH
• Application Number:
  US10/315,156
• Publication Number:
  US 20030065966A1
• Time in Patent Office: 560 Days
• Field of Search: 713/500, 713/501, 713/600, 370/507
• US Class Current: 713/500
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 21/725 operating on a secure reference time value

Abstract

An over-clock deterrent mechanism of a chipset which comprises an over-clock detection circuit for detecting over-clocking of a system (processor) clock signal based on comparison of ratio of the system (processor) clock signal which is likely to be over-clocked and a fixed, stable reference clock signal which is highly unlikely to be over-clocked, and an over-clock prevention (thwarting) circuit for deterring such an over-clocking by either disabling operations of a computer system or significantly undermining key operations of a computer system.

Claims

1. A system, comprising:

a clock generator to generate a clock signal;

a device operable based on the clock signal; and

an over-clock deterrent mechanism for detecting and deterring over-clocking of the clock signal, the over-clock deterrent mechanism comprising;

a detection circuit to detect over-clocking of the clock signal based on a reference signal;

a prevention circuit to prevent over-clocking of the clock signal by either disabling operations of the device or limiting performance of the device in response to detection of said over-clocking of the clock signal; and

a status register to store software readable status bits indicating if the clock signal is either over-clocked or under-clocked for software diagnostics purposes.

2. The system as claimed in claim 1, wherein the detection circuit comprises:

quartz crystal to generate the reference signal exhibiting a fixed dock frequency;

a counter to count the clock signal relative to the reference signal and to produce a counter value;

a comparator to determine whether the clock signal has an over-clocking condition based on the counter value with a predetermined ratio; and

latches to latch comparator outputs indicating at least whether said over-clocking condition has been detected.

3. The system as claimed in claim 2, wherein the counter is clocked by the clock signal, and is set or reset to zero (0) by a rising edge of a clock of the reference signal.

4. The system as claimed in claim 2, wherein the comparator determines said over-clocking condition when the counter value reaches a maxim allowed ratio, and an under-clocking condition when the counter value is below a minimum allowed ratio.

5. The system as claimed in claim 2, wherein the detection circuit comprises:

a ring oscillator to generate the reference signal exhibiting a fixed clock frequency;

a counter to count the clock signal relative to the reference signal and produce a counter value;

a comparator to determine whether the clock signal has an over-clocking condition based on the counter value with a predetermined ratio; and

latches to latch comparator outputs indicating at least whether said over-clocking condition has been detected.

6. The system as claimed in claim 2, wherein the prevention circuit comprises a power supply control logic circuit to deactivate a power supply from attending to the device and disabling operations of the device, when said over-clock condition has been detected.

7. The system as claimed in claim 2, wherein the prevention circuit comprises a thermal control logic circuit to assert a stop clock signal to the device to halt the device temporarily from operations, when an over-clock condition has been detected.

8. The system as claimed in claim 2, wherein the prevention circuit comprises a frequency select circuit to assert a frequency select signal to the device to reduce an operation frequency of the device, when an over-clock condition has been detected.

9. A system comprising:

a clock generator to generate a clock signal;

a host device operable to process information based on the clock signal;

a chipset coupled to the host device to control operations of the host device in response to the clock signal and provide an interface with a plurality of I/O devices, said chipset comprising;

a mechanism to determine whether the clock signal is either over-clocked or under-clocked; and

a status register to store status bits indicating if the clock signal is over-clocked or under-clocked.

10. The system as claimed in claim 9, wherein said mechanism for determining whether the clock signal is over-clocked or under-clocked comprises:

a detection circuit to detect whether the clock signal is over-clocked or under-clocked based on a reference signal; and

a prevention circuit to prevent over-clocking of the clock signal by either disabling operations of the host device or reducing performance of the host device, when the clock signal is over-clocked.

11. The system as claimed in claim 10, wherein the detection circuit comprises:

a quartz crystal to generate the reference clock signal exhibiting a fixed clock frequency;

a counter to count cycles of the clock signal relative to the reference signal and to produce a counter value;

a comparator to determine whether the clock signal is over-clocked or under-clocked based on the counter value with a predetermined ratio; and

latches to latch comparator outputs indicating at least whether the clock signal is over-clocked or under-clocked.

12. The system as claimed in claim 11, wherein the detection circuit comprises:

a ring oscillator to generate the reference signal exhibiting a fixed clock frequency;

a counter to count cycles of the clock signal relative to the reference signal and to produce a counter value;

a comparator to determine whether the clock signal is over-clocked or under-clocked based on the counter value with a predetermined ratio; and

latches to latch comparator outputs indicating at least whether the clock signal is over-clocked or under-clocked.

13. The system as claimed in claim 11, wherein the prevention circuit comprises a power supply control logic circuit to deactivate power supply from attending to the host device and disables operations of the host, when said clock signal is over-clocked.

14. The system as claimed in claim 11, wherein the prevention circuit comprises a thermal control logic circuit to assert a stop clock signal to the host device to halt the host device temporarily from operations, when the clock signal is over-clocked.

15. The system as claimed in claim 11, wherein the prevention circuit comprises a frequency select circuit to assert a frequency select signal to the host device to reduce an operation frequency of the host device, when the clock signal is over-clocked.

16. A method for detecting over-clocking and/or under-clocking of a clock signal of a host device, comprising:

loading an operating system and executing an initialization sequence;

reading software status register bits to determine whether a clock signal is over-clocked or under-clocked;

indicating that the host device is not serviceable if the software readable register bits indicated that the clock signal is over-clocked;

determining whether the clock signal is under-clocked if the software readable register bits indicated that the clock signal is not over-clocked;

providing software diagnostics if the software readable register bits indicate that the clock signal is not under-clocked; and

indicating that clock generation of the host device contains defects if the software readable register bits indicated that the clock signal is under-clocked.

17. A system comprising:

a clock generator to generate a clock signal for data processing operations;

a device operable to process data information based on the clock signal;

a chipset coupled to the device which comprises a reference signal for providing real-time clock, and an over-clock deterrent mechanism for detecting over-clocking of the clock signal based on the reference signal, and deterring said over-clocking of the clock signal by either disabling operations of the device or reducing performance of the device in response to detection of said over-clocking of the clock signal.

18. The system as claimed in claim 17, wherein said chipset further comprises a status register to store software readable status bits which indicated if the clock signal is either over-clocked or under-clocked for software diagnostics.

19. The system as claimed in claim 17, wherein the over-clock deterrent mechanism comprises:

a counter to count cycles of the clock signal relative to the reference signal and to produce a counter value;

a comparator to determine whether the clock signal has an over-clocking condition based on the counter value with a predetermined ratio;

latches to latch comparator outputs indicating at least whether said over-clocking condition has been detected; and

a power supply control logic circuit to deactivate power supply from attending to the device and disables operations of the device, when said over-clock condition has been detected.

20. The system as claimed in claim 17, wherein the over-clock deterrent mechanism comprises:

a counter to count cycles of the clock signal relative to the reference signal and to produce a counter value;

a comparator to determine whether the clock signal has an over-clocking condition based on the counter value with a determined ratio;

latches to latch comparator outputs indicating at least whether said over-clocking condition has been detected; and

a thermal control logic circuit to assert a stop clock signal to the device so as to halt the device temporarily from operations, when said over-clock condition has been detected.

21. The system as claimed in claim 17, wherein the over-clock deterrent mechanism comprises:

a counter to count cycles of the clock signal relative to the reference signal and to produce a counter value;

a comparator to determine whether the clock signal has an over-clocking condition based on the counter value with a predetermined ratio;

latches to latch comparator outputs indicating at least whether said over-clocking condition has been detected; and

a frequency select circuit to assert a frequency select signal to the processor so as to reduce an operation frequency of the device, when an over-clock condition has been detected.