Method of and apparatus for testing CPU built-in RAM mixed LSI

• US 6,754,849 B2
• Filed: 07/16/2001
• Issued: 06/22/2004
• Est. Priority Date: 03/09/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Tamura, Hiroaki
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): Wilson, Yolanda L
• Application Number:
  US09/904,507
• Publication Number:
  US 20020129298A1
• Time in Patent Office: 1,072 Days
• Field of Search: 714/30, 714/25, 714/42, 714/718, 714/719
• US Class Current: 714/30
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

A test apparatus includes a switch switched towards the ROM under the control of a signal output from the tester. When the switch is switched towards the ROM, the computer program for carrying out the self test is loaded in the main memory and the CPU performs the test using this computer program.

Claims

1. A test apparatus for a CPU built-in RAM mixed LSI for self-testing mixed RAM of the CPU built-in RAM mixed LSI mounted onto a test board using a tester, including a test board on which are mounted

a ROM in which a self test program for conducting a self test by access between a built-in CPU and the mixed RAM of the CPU built-in RAM mixed LSI is stored, and

a ROM switching unit for switching between a signal from the tester to the CPU built-in RAM mixed LSI and a signal from the ROM to the CPU built-in RAM mixed LSI and inputting the switched signal into signal terminals of the CPU built-in RAM mixed LSI, wherein, after the ROM switching unit is switched to a ROM side by using the tester, the self test program is loaded from the ROM into a main memory connected to the built-in CPU for conducting the self test.

2. The test apparatus according to claim 1, wherein the self test includes a test including a surround disturb pattern.

3. The test apparatus according to claim 1 further comprising a socket into which said ROM can be detachably fixed, mounted on said test board.

4. The apparatus according to claim 1 further comprising a second switching unit for establishing a connection between said tester and said ROM.

5. The apparatus according to claim 1 further comprising:

an oscillator for generating a clock signal desired frequency; and

a clock switching unit for connecting a clock signal output by said tester to the CPU built-in RAM mixed LSI, and for connecting a clock signal output by said oscillator to the CPU built-in RAM mixed LSI, wherein said oscillator and said clock switching unit are mounted on said test board.

6. The apparatus according to claim 1 further comprising:

a debug tool connector for connecting a debug tool; and

a debug signal switching unit connecting a debug signal output by said tester to the CPU built-in RAM mixed LSI, and connecting a connection between a debug signal output by said debug tool connected to said connector and the CPU built-in RAM mixed LSI, wherein said debug tool connector and said debug signal switching unit are mounted on said test board.

7. A method of self-testing a mixed RAM of a CPU built-in RAM mixed LSI mounted onto a test board using a tester, the method comprising:

mounting a ROM on a test board, wherein said ROM stores a self test program for conducting a self test by access between a built-in CPU and the mixed RAM of the CPU built-in RAM mixed LSI;

mounting a ROM switching unit on the test board, wherein said ROM switching unit switches between a signal from said tester to said CPU built-in RAM mixed LSI and a signal from said ROM to said CPU built-in RAM mixed LSI and receives the switched signal into signal terminals of said CPU built-in RAM mixed LSI; and

switching said ROM switching unit to said ROM side using said tester and loading the self test program from said ROM into a main memory connected to said built-in CPU for conducting the self test.

8. A test apparatus for self-testing a mixed RAM of a CPU built-in RAM mixed LSI, said apparatus comprising:

a tester that includes

a signal generation unit which generates at least a switching signal;

a switching signal output terminal through which the switching signal is output; and

a signal output terminal through which a signal is output,

a test board on which is mounted

a ROM that stores a computer program which, when executed, conducts the self test by access from said CPU of said LSI to said mixed RAM; and

a switching unit which, under control of the switching signal output from said switching signal output terminal, establishes a signal path between said LSI and one of said signal output terminal of said tester and said ROM, wherein said CPU of said LSI loads the computer program stored in said ROM into a main memory when said switching unit establishes a signal path between said LSI and said ROM.