Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)

• US 6,754,882 B1
• Filed: 02/22/2002
• Issued: 06/22/2004
• Est. Priority Date: 02/22/2002
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Sanchez, Reno L., Linn, John H.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Dinh, Paul
• Application Number:
  US10/082,440
• Time in Patent Office: 851 Days
• Field of Search: 716/1, 716/4, 716/16-18, 326/39, 703/13-14
• US Class Current: 716/117
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level

Abstract

A method for customization of the software of an FPGA-based SoC includes the steps of selecting (380) a system component used for customizing the FPGA-based SoC, configuring (382) the selected system component with parameters for use with the FPGA-based SoC and propagating (384) the parameters used to configure the selected system component to peer system components. The method further includes the step of configuring (388) the peer system components using the propagated parameters during customization of the FPGA-based SoC and creating (401) a software interface to the selected system components and to the peer system components.

Claims

1. A method for customization of the software of an FPGA-based SoC, the method comprising:

selecting a system component used for customizing the FPGA-based SoC;

configuring said selected system component with parameters for use with the FPGA-based SoC;

propagating said parameters used to configure said selected system component to peer system components;

configuring said peer system components using said propagated parameters during customization of the FPGA-based SoC;

creating a software interface to said selected system component and to said peer system components.

2. The method according to claim 1, further comprising configuring the selected system component with parameters used to configure said peer system component.

3. The method according to claim 2, further comprising the step of propagating said parameter used to configure said peer system component to subsequently selected system components used to configure the software of the FPGA-based SoC.

4. The method according to claim 1, wherein the method further comprises the step of initializing only the selected system components that are utilized for customizing the FPGA-based SoC.

5. The method of claim 1, wherein the step of creating a software interface comprises the step of creating a board support package which contains a chip support package providing a software interface to hardware functions selected from the group comprising hardware initialization, interrupt handling, interrupt generation, hardware clock management, hardware timer management, mapping of local and bus memory spaces, and memory sizing.

6. The method of claim 1, wherein the step of creating a software interface further comprises the step of determining at an initialization of the FPGA-based SoC which selected system components and peer components are present on the FPGA-based SoC.

7. A method for customizing software of a system including an FPGA-based SoC, the method comprising:

selecting a system component used for customizing the FPGA-based SoC;

configuring the selected system component with parameters for use with the FPGA-based SoC;

propagating the parameters used to configure the selected system component to peer system components;

configuring the peer system components using the propagated parameters during customization of the FPGA-based SoC;

creating a software interface to the system by creating a software interface to the selected system component and to the peer system components.

8. The method of claim 7, wherein the system further includes a microprocessor coupled to the FPGA-based SoC.

9. The method of claim 7, wherein the FPGA-based SoC is an FPGA-based embedded processor SoC.