Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance

• US 6,756,274 B2
• Filed: 05/14/2002
• Issued: 06/29/2004
• Est. Priority Date: 04/22/1999
• Status: Expired due to Term

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Grabowski, Wayne, Williams, Richard K.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US10/146,568
• Publication Number:
  US 20020168821A1
• Time in Patent Office: 777 Days
• Field of Search: 438/212, 438/268, 438/270, 438/272, 438/430, 438/431
• US Class Current: 438/270
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Claims

1. A method for fabricating a trench MOSFET comprising:

forming a first mask over a surface of a body of semiconductor material, the first mask having an opening where a trench is to be located in the body;

etching the semiconductor material through the opening in the first mask to form a trench in the semiconductor body;

forming a first oxide layer in the trench, wherein forming the first oxide layer comprises;

depositing an oxide in the trench, the oxide filling at least a portion of the trench;

etching the oxide to remove the oxide from an upper portion of sidewalls of the trench and leave a bottom oxide layer on a bottom of the trench, the bottom oxide layer having a substantially flat top surface extending between the sidewalls of the trench; and

forming a sidewall oxide layer on the upper portion of the sidewalls of the trench, the sidewall oxide layer being thinner than the bottom oxide layer;

introducing a first polysilicon layer into the trench;

with the first mask in place, oxidizing an exposed surface of the first polysilicon layer to form a second oxide layer at the top of the trench, the second oxide layer extending down into the trench;

introducing dopant of a first conductivity type into the body to form a body region, a junction of the body region being at a level with the top surface of the bottom oxide layer;

removing the first mask; and

depositing a metal layer on a surface of the second oxide layer and the surface of the body.

2. The method of claim 1, wherein forming a first mask comprises depositing a nitride layer.

3. The method of claim 2, further comprising forming a third oxide layer between the surface of the body and the nitride layer.

4. The method of claim 3, wherein at least a portion of the third oxide layer remains after the first mask is removed.

5. The method of claim 4, further comprising removing the third oxide layer.

6. The method of claim 3, wherein the second oxide layer is thicker than the third oxide layer.

7. The method of claim 1, wherein the second oxide layer is thicker than the sidewall oxide layer.

8. The method of claim 1, wherein depositing oxide in the trench comprises depositing oxide by a chemical vapor deposition process.

9. The method of claim 1, further comprising removing a top portion of the first polysilicon layer so that a top surface of the first polysilicon layer is lower than a top surface of the mask.

10. The method of claim 9, wherein the top surface of the first polysilicon layer is coplanar with the surface of the body.

11. The method of claim 1, wherein the body of semiconductor material comprises an epitaxial layer on a surface of a semiconductor substrate.

12. The method of claim 11, wherein introducing dopant of the first conductivity type into the body comprises implanting dopant of the first conductivity type through a solid portion of the first mask to form the body region in the epitaxial layer.

13. The method of claim 12, further comprising implanting dopant of a second conductivity type through the solid portion of the first mask to form a source region in the epitaxial layer.

14. The process of claim 1, further comprising forming a second trench in the semiconductor body so as to form a mesa between the trench and the second trench.

15. The process of claim 14, wherein depositing a metal layer comprises depositing a metal layer that is in contact with substantially the entire surface of the mesa between the trenches.

16. The process of claim 14, wherein the first trench, the second trench, and the mesa have the same width.

17. The method of claim 1, wherein the second oxide layer is thicker than the sidewall oxide layer.

18. The method of claim 1, wherein before depositing the oxide, the method further comprises:

oxidizing the sidewalls and the bottom of the trench; and

removing an oxide layer that results from the oxidizing.

19. A method of fabricating a MOSFET, comprising:

forming a trench and a mesa adjacent to the trench in a surface of a semiconductor body;

forming a first insulating layer along a wall of the trench;

forming a gate in the trench, the gate being insulated from the semiconductor body by the first insulating layer;

implanting a dopant of a first conductivity type into the mesa to form a body region;

implanting a dopant of a second conductivity type into the mesa to form a source region;

forming a second insulating layer over the mesa;

forming a mask having an opening defining an area of a contact opening to be formed in the second insulating layer;

etching the second insulating layer through the mask to form the contact opening in the second insulating layer; and

depositing a metal layer into the contact opening to form an electrical contact with the source region, the depositing being carried out at a pressure greater than atmospheric pressure.

20. The method of claim 19, wherein depositing the metal layer is performed at a pressure of about two atmospheric pressures.

21. The method of claim 19, further comprising depositing a barrier layer on a surface of the mesa.

22. The method of claim 19, wherein the depositing is by a process selected from the group consisting of sputtering, evaporation, chemical vapor deposition, and plasma-enhanced chemical vapor deposition and being performed.

23. The method of claim 19, wherein the-pressure greater than atmospheric pressure helps to force metal ions into the contact opening during depositing of the metal layer.

24. A method of fabricating a MOSFET comprising:

forming a trench in a surface of a semiconductor body, the trench defining a mesa;

forming a first insulating layer including a bottom layer at a bottom of the trench and a sidewall layer along a wall of the trench, wherein the bottom layer is thicker than the sidewall layer;

introducing a polysilicon layer into the trench, an exposed surface of the polysilicon layer being substantially coplanar with a surface of the semiconductor body;

oxidizing the exposed surface of the polysilicon layer to form an oxide layer at the top of the trench, the oxide layer extending down into the trench;

implanting a dopant of a first conductivity type into the mesa to form a body region with a junction at substantially the same level as a top surface of the bottom layer in the trench;

implanting a dopant of a second conductivity type into the mesa to form a source region;

forming a second insulating layer over the polysilicon layer and the mesa;

etching an opening in the second insulating layer over the mesa;

depositing a first metal layer into the opening to form an electrical contact with the source region;

planarizing the first metal layer to form a plug, a surface of the plug being coplanar with a surface of the second insulating layer; and

depositing a second metal layer over the second insulating layer and the plug.

25. The method of claim 24, wherein forming a second insulating layer comprises forming a glass layer.

26. The method of claim 24, wherein depositing a first metal layer comprises depositing a metal from the group consisting of tungsten and copper.

27. The method of claim 24, wherein planarizing the first metal layer comprises chemical-mechanical polishing.

28. The method of claim 24, wherein planarizing the first metal layer comprises etching.

29. The method of claim 24, wherein the source region and the body region have respective contact areas at a flat top surface of the mesa.