Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals

• US 6,756,298 B2
• Filed: 08/01/2002
• Issued: 06/29/2004
• Est. Priority Date: 01/18/2000
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US10/211,855
• Publication Number:
  US 20020197850A1
• Time in Patent Office: 698 Days
• Field of Search: 438/653, 438/654, 438/656, 438/688, 438/243, 438/244, 438/386, 438/685, 438/785, 438/791, 438/608, 438/635, 257/77, 257/750, 257/754, 257/742, 257/770, 257/762
• US Class Current: 438/635
• CPC Class Codes: C23C 14/3471 Introduction of auxiliary energy into the plasma
• CPC Class Codes: C23C 16/517 using a combination of discharges covered by two or more of groups C23C16/503 - C23C16/515
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01J 37/3408 Planar magnetron sputtering
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles. Accordingly, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers. One embodiment of the wafer-processing chamber includes equipment for physical vapor deposition and equipment for chemical vapor deposition to facilitate formation of diffusion barriers and seed layers within one chamber, thereby promoting fabrication efficiency and reducing defects.

Claims

1. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen; and

a layer comprising a silver- or gold-based material.

4. The integrated circuit of claim 1, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms.

5. The integrated circuit of claim 1, further comprising two or more memory cells.

2. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen; and

a layer comprising a silver-based material.

6. The integrated circuit of claim 2, further comprising two or more memory cells.

7. The integrated circuit of claim 2, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms.

3. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen; and

a layer comprising a gold-based material.

8. The integrated circuit of claim 3, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms.

9. The integrated circuit of claim 3, further comprising two or more memory cells.

10. An integrated circuit comprising

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen; and

a layer comprising a silver- or gold-based material, with the layer comprising tungsten, silicon, and nitrogen between the layer comprising a silver- or gold-based material and the insulative layer.

11. The integrated circuit of claim 10, further comprising two or more memory cells.

12. The integrated circuit of claim 10, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms.

13. An integrated circuit comprising

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen, wherein the layer comprising tungsten, silicon, and nitrogen comprises a graded composition of tungsten silicide; and

a layer comprising a silver- or gold-based material.

14. The integrated circuit of claim 13, further comprising two or more memory cells.

15. The integrated circuit of claim 13, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms.

16. An integrated circuit comprising

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen, wherein the layer comprising tungsten, silicon, and nitrogen comprises a graded composition of WSi_x, with x varying from 2.0 to 2.5; and

a layer comprising a silver- or gold-based material.

17. The integrated circuit of claim 16, further comprising two or more memory cells.

18. The integrated circuit of claim 16, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms.

19. An integrated circuit comprising

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen, wherein the layer comprising tungsten, silicon, and nitrogen comprises a graded composition of WSi_x, with x varying from 2.0 to 2.5, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms; and

a layer comprising a silver- or gold-based material.

20. The integrated circuit of claim 19, further comprising two or more memory cells.

21. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen; and

a layer comprising a silver-based material, with the layer comprising tungsten, silicon, and nitrgen between the layer comprising a silver-based material and the insulative layer.

22. The integrated circuit of claim 21, further comprising two or more memory cells.

23. The integrated circuit of claim 21, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms.

24. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen, wherein the layer comprising tungsten, silicon, and nitrogen comprises a graded composition of tungsten silicide; and

a layer comprising a silver-based material.

25. The integrated circuit of claim 24, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms.

26. The integrated circuit of claim 24, further comprising two or more memory cells.

27. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen, wherein the layer comprising tungsten, silicon, and nitrogen comprises a graded composition of WSi_x, with x varying from 2.0 to 2.5; and

a layer comprising a silver-based material.

28. The integrated circuit of claim 27, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms.

29. The integrated circuit of claim 27, further comprising two or more memory cells.

30. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen, wherein the layer comprising tungsten, silicon, and nitrogen comprises a graded composition of WSi_x, with x varying from 2.0 to 2.5, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms; and

a layer comprising a silver-based material.

31. The integrated circuit of claim 30, further comprising two or more memory cells.

32. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen; and

a layer comprising a gold-based material, with the layer comprising tungsten, silicon, and nitrogen between the layer comprising a gold-based material and the insulative layer.

33. The integrated circuit of claim 32, further comprising two or more memory cells.

34. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen, wherein the layer comprising tungsten, silicon, and nitrogen comprises a graded composition of tungsten silicide; and

a layer comprising a gold-based material.

35. The integrated circuit of claim 34, further comprising two or more memory cells.

36. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen, wherein the layer comprising tungsten, silicon, and nitrogen comprises a graded composition of WSi_x, with x varying from 2.0 to 2.5; and

a layer comprising a gold-based material.

37. The integrated circuit of claim 36, further comprising two or more memory cells.

38. An integrated circuit comprising:

a layer including one or more transistors;

an insulative layer overlying the layer and having one or more conductive structures, with each conductive structure electrically coupled to one or more of the transistors and comprising;

a layer comprising tungsten, silicon, and nitrogen, wherein the layer comprising tungsten, silicon, and nitrogen comprises a graded composition of WSi_x, with x varying from 2.0 to 2.5, wherein the layer comprising tungsten, silicon, and nitride comprises a layer of tungsten silicide having interstitial sites stuffed with nitrogen atoms; and

a layer comprising a gold-based material.

39. The integrated circuit of claim 38, further comprising two or more memory cells.