Embedded electrically programmable read only memory devices

• US 6,756,645 B2
• Filed: 04/23/2002
• Issued: 06/29/2004
• Est. Priority Date: 01/11/2000
• Status: Expired due to Fees

• Current Assignee: Jeng-Jye Shau
• Original Assignee: Jeng-Jye Shau
• Inventors: Shau, Jeng-Jye
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US10/127,953
• Publication Number:
  US 20020173101A1
• Time in Patent Office: 798 Days
• Field of Search: 257/390, 257/391, 257/294, 257/295, 257/306, 257/315, 257/297, 257/298, 257/299, 257/300, 257/307, 257/308, 257/311, 257/314, 257/316, 257/317, 257/318, 257/319, 257/320, 257/321, 257/322, 257/323
• US Class Current: 257/391
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention teaches novel electrically programmable read only memory (EPROM) devices for embedded applications. EPROM devices of the present invention utilize existing circuit elements without complicating existing manufacture technologies. They can be manufactured by dynamic random access memory (DRAM) technologies, standard logic technologies, or any type of IC manufacture technologies. Unlike conventional EPROM devices, these novel devices do not require high voltage circuits to support their programming operation. EPROM devices of the present invention are ideal for embedded applications. Typical applications including the redundancy circuits for DRAM, the programmable firmware for logic products, and the security identification circuits for IC products.

Claims

1. An EPROM device comprises

a plurality of active circuit elements;

and

a stress means to apply electrical stresses to change an active performance characteristic of said active circuit elements and wherein said active circuit elements further comprising bipolar transistors.

2. The EPROM device of claim 1 further comprising:

a sensing means to sense a change of a current versus voltage variation (Δ

i/Δ

v) performance characteristic of said active circuit elements.

3. The EPROM device of claim 1 wherein:

said active circuit elements are MOS transistors.

4. The EPROM device of claim 1 further comprising:

dynamic random access memory (DRAM) cells disposed adjacent to said EPROM device.

5. The EPROM device of claim 1 wherein:

said active circuit elements are diodes.

6. The EPROM device of claim 1 wherein:

said active circuit elements further comprising transistors and said stress means is provided to cause hot carrier stress to cause a change of a drain-source current response characteristic to a gate-drain voltage of said active circuit elements.

7. The EPROM device of claim 1 wherein:

said active circuit elements further comprising transistors and said stress means is provided to apply high voltage to cause a change of a drain-source current response characteristic to a gate-drain voltage of said active circuit elements.

8. A stress effect programmable read only memory (SEPROM) device comprising:

a stress circuit having an electrically-stressed operational characteristic and a reference electric circuit having a reference operational characteristic; and

a sense circuit for sensing a difference between said stress operational characteristic and said reference operational characteristic for detecting a data stored in said SEPROM.

9. The SEPROM of claim 8 wherein:

said stress circuit comprising an array of electrically-stressed transistors and said reference circuit comprising an array of reference transistors.

10. The SEPROM of claim 8 wherein:

said stress circuit comprising an array of electrically-stressed diodes and said reference circuit comprising an array of reference diodes.

11. The SEPROM of claim 8 wherein:

said stress circuit comprising an array of electrically-stressed bipolar transistors and said reference circuit comprising an array of reference bipolar transistors.