Noise eliminating system on chip and method of making same

• US 6,756,664 B2
• Filed: 04/07/2003
• Issued: 06/29/2004
• Est. Priority Date: 11/22/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Yang, Chih An
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US10/407,231
• Publication Number:
  US 20040099934A1
• Time in Patent Office: 449 Days
• Field of Search: 257/691, 257/723, 257/724, 257/659, 257/307, 257/516, 257/777, 438/109, 438/110
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15184 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19104 on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A noise eliminating system on chip and method of fabricating the same are provided. A noise eliminating system is connected to a chip. There are guiding units provided on the chip for connecting with the noise eliminating system, thereby reducing simultaneous switching noise of the chip.

Claims

1. A noise eliminating system on chip, comprising:

a chip;

a power supply unit provided on the chip and being electrically connected to the chip;

a grounding unit provided on the chip and being electrically connected to the chip;

a guiding unit installed on an upper surface of the chip and being electrically connected to the power supply unit and the grounding unit; and

at least one noise eliminating system comprising a connecting unit and a noise eliminating unit, wherein the connecting unit is electrically connected to the noise eliminating unit, and wherein the connecting unit is electrically connected to the guiding unit.

2. The noise eliminating system on chip as claimed in claim 1 wherein a protection layer is provided on the guiding unit and the chip, and a guiding unit opening is provided at the joint between the guiding unit and the connecting unit of the noise eliminating system.

3. The noise eliminating system on chip as claimed in claim 1 wherein the guiding unit comprises at least one first guiding device and at least one second guiding device, which are installed in a first region and second region of the chip respectively, and wherein the first guiding device is electrically connected to the power supply unit and the second guiding device is electrically connected to the grounding unit.

4. The noise eliminating system on chip as claimed in claim 3 wherein the a first guiding device opening e and a second guiding device opening corresponding to the first guiding device in the first region and the second guiding device in the second region respectively are provided in the protection layer that covers the guiding unit and the chip.

5. The noise eliminating system on chip as claimed in claim 4 wherein the connecting unit of the noise eliminating system comprises two connecting ports which protrude through respective first and second guiding openings to electrically connect to the first and second guiding devices.

6. The noise eliminating system on chip as claimed in claim 3 wherein the first and second regions are located on the chip.

7. The noise eliminating system on chip as claimed in claim 3 wherein the guiding device is a circuit.

8. The noise eliminating system on chip as claimed in claim 1 wherein the noise eliminating system is a passive component.

9. The noise eliminating system on chip as claimed in claim 1 wherein the noise eliminating system is a de-coupling capacitor.

10. A method for fabricating a noise eliminating system on chip, comprising the steps of:

providing a chip having thereon a power supply unit and a grounding unit;

forming a guiding device layer on an upper surface of the chip;

etching the guiding device layer to form the guiding devices;

providing a noise eliminating system;

using surface mount technology to install the noise eliminating system on the upper surface of the chip, and the noise eliminating system connects to the guiding devices; and

jointing the junction between the noise eliminating system and the guiding devices such that the noise eliminating system is electrically connected to the guiding devices.

11. The method for fabricating a noise eliminating system on chip as claimed in claim 10 wherein the guiding device layer is made of conductive material sputtered on the upper surface of the chip.

12. The method for fabricating a noise eliminating system on chip as claimed in claim 10 wherein the noise eliminating system is a passive component.

13. The method for fabricating a noise eliminating system on chip as claimed in claim 10 wherein the noise eliminating system is a de-coupling capacitor.

14. The method for fabricating a noise eliminating system on chip as claimed in claim 10 wherein the guiding devices are circuit layers inside the chip.