Flip-chip ball grid array semiconductor package with heat-dissipating device and method for fabricating the same

• US 6,756,684 B2
• Filed: 07/10/2002
• Issued: 06/29/2004
• Est. Priority Date: 02/05/2002
• Status: Expired due to Term

• Current Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Original Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Inventors: Huang, Chien-Ping
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/192,399
• Publication Number:
  US 20030146519A1
• Time in Patent Office: 720 Days
• Field of Search: 257/723, 257/778, 257/781, 257/712, 257/717, 324/765
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/3738 Semiconductor materials
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A FCBGA (flip-chip ball grid array) semiconductor package with a heat-dissipating device and a method for fabricating the same are provided. At least a chip is mounted on a substrate in a flip-chip manner, and connected to a heat-dissipating device that is composed of a heat sink and a plurality of thermally conductive bumps implanted on the beat sink. Heat produced from the chip is dissipated via the heat-dissipating device. The thermally conductive bumps are bonded to a circuit board, and thereby reduce contact area between the heat-dissipating device and the circuit board, without forming of voids or popcorn effect during a solder-reflow process. The heat sink in contact with the chip is similar in coefficient of thermal expansion (CTE) to the chip, so as to prevent delamination between the heat sink and the chip, thereby assuring quality and yield of fabricated package products.

Claims

1. A FCBGA (flip-chip ball grid array) semiconductor package with a heat-dissipating device, the FCBGA semiconductor package comprising:

a substrate having an upper surface and a lower surface opposed to the upper surface;

at least one first chip mounted on and electrically connected to the upper surface of the substrate;

at least one second chip mounted on the lower surface of the substrate in a flip chip manner, the second chip having an active surface and a non-active surface opposed to the active surface, allowing the second chip to be electrically connected to the substrate by bonding a plurality of first conductive elements to the active surface of the second chip and the lower surface of the substrate;

a plurality of second conductive elements implanted on the lower surface of the substrate at an area exclusive of the second chip; and

a heat-dissipating device composed of a heat sink and a plurality of thermally conductive bumps, wherein the heat sink has an upper surface and a lower surface opposed to the upper surface, allowing the upper surface to be attached to the non-active surface of the second chip, and the thermally conductive bumps are implanted on the lower surface of the heat sink.

2. The FCBGA semiconductor package of claim 1, wherein the first chip is electrically connected to the substrate by a plurality of bonding wires, and the first chip and the bonding wires are encapsulated by an encapsulant formed on the upper surface of the substrate.

3. The FCBGA semiconductor package of claim 1, wherein the first conductive elements between the second chip and the substrate are encapsulated by underfill technology.

4. The FCBGA semiconductor package of claim 1, wherein the thermally conductive bumps and the second conductive elements are simultaneously mounted on a circuit board that is formed with a plurality of thermal vias connected to the thermally conductive bumps in a manner that, the thermally conductive bumps are interposed between the heat sink and the circuit board, and the second conductive elements are interposed between the substrate and the circuit board.

5. The FCBGA semiconductor package of claim 1, wherein combined thickness of the second chip, first conductive element, heat sink and thermally conductive bump is equal to height of the second conductive element.

6. The FCBGA semiconductor package of claim 1, wherein combined thickness of the second chip, first conductive element, heat sink and thermally conductive bump is smaller than height of the second conductive element.

7. The FCBGA semiconductor package of claim 1, wherein the heat sink is made of silicon.

8. The FCBGA semiconductor package of claim 1, wherein the heat sink comprises a BT (bismaleimide triazine) resin layer formed with a plurality of vias 244, and a copper layer formed over a surface of the BT resin layer, allowing the thermally conductive bumps to be implanted on an opposed surface of the BT resin layer and connected to the vias.

9. The FCBGA semiconductor package of claim 1, wherein the heat sink comprises a polyimide tape formed with a plurality of through holes, and a copper layer formed over a surface of the polyimide tape, allowing the thermally conductive bumps to be implanted on an opposed surface of the polyimide tape and connected to the copper layer via the through holes.

10. The FCBGA semiconductor package of claim 1, wherein the heat sink is formed with at least one protruding portion peripherally protruding from the upper surface of the heat sink toward the substrate to reach the lower surface of the substrate.

11. The FCBGA semiconductor package of claim 1, wherein the first and second conductive elements are solder bumps.