Customizable and programmable cell array

• US 6,756,811 B2
• Filed: 03/12/2001
• Issued: 06/29/2004
• Est. Priority Date: 03/10/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi
• Primary Examiner(s): LE, DON P
• Application Number:
  US09/803,373
• Publication Number:
  US 20010038297A1
• Time in Patent Office: 1,205 Days
• Field of Search: 326/37-41, 326/101-103
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H03K 19/1732 by limitation or reduction of the pin/gate ratio for data-processing equipment G06F1/22
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A personalizable and programmable integrated circuit device including at least first and second programmable logic cells and at least one permanent electrical conductive path interconnecting the at least first and second programmable logic cells for personalization of the integrated circuit device, wherein the at least first and second programmable logic cells are programmable by the application of an electrical signal thereto.

Claims

1. A section of an integrated circuit device comprising at least first, second and third metal layers and a first via layer to provide connection between said first metal layer and said second metal layer and a second via layer to provide connection between said second metal layer and said third metal layer,

wherein at least each of said first metal and said second metal layers consists of a repeating pattern, and wherein at least one of said first via, second via and third metal layers comprises a custom pattern designed to customize the integrated circuit device to a specific user'"'"'s needs, wherein said first metal layer repeating pattern comprises strips extending generally in parallel to a first axis, and wherein said strips are stepped strips.

2. A section of an integrated circuit device comprising at least first, second and third metal layers and a first via layer to provide connection between said first metal layer and said second metal layer and a second via layer to provide connection between said second metal layer and said third metal layer,

wherein at least each of said first metal and said third metal layers consists of a repeating pattern, and wherein at least one of said first via, second via and second metal layers comprises a custom pattern designed to customize the integrated circuit device to a specific user'"'"'s needs, wherein said third metal layer repeating pattern comprises strips extending generally in parallel to a first axis, and wherein said strips are stepped strips.

3. A section of an integrated circuit device comprising at least first, second and third metal layers and a first via layer to provide connection between said first metal layer and said second metal layer and a second via layer to provide connection between said second metal layer and said third metal layer,

wherein at least each of said first metal and said second metal layers consists of a repeating pattern, and wherein at least one of said first via, second via and third metal layers comprises a custom pattern designed to customize the integrated circuit device to a specific user'"'"'s needs, wherein said first metal layer repeating pattern comprises strips extending generally in parallel to a first axis, wherein at least two vias of first via layer are overlying at least one of said strips connecting said strips to second metal layer, and wherein said at least two vias are in propinquity to a beginning and an end of said at least one of said strips.

4. A device according to claim 3 and wherein said strips are in a band of generally equal length strips.

5. A section of an integrated circuit device according to claim 3, and further comprising:

at least first and second programmable logic cells; and

at least one permanent electrical conductive path interconnecting said at least first and second programmable logic cells for customizing said device to a specific user'"'"'s needs.

6. A section of an integrated circuit device according to claim 3, and further comprising:

a logic cell array including a multiplicity of logic cells, wherein said logic cell comprises at least one look-up table.

7. A section of an integrated circuit device according to claim 3, and further comprising:

a logic cell array including a multiplicity of logic cells, wherein said logic cell comprises at least one flip-flop.

8. A section of an integrated circuit device according to claim 5, and wherein said custom pattern is prepared with direct write e-beam lithography.

9. A section of an integrated circuit device according to claim 6, and wherein said custom pattern is prepared with direct write e-beam lithography.

10. A section of an integrated circuit device according to claim 7, and wherein said custom pattern is prepared with direct write e-beam lithography.

11. A section of an integrated circuit device comprising at least first, second and third metal layers and a first via layer to provide connection between said first metal layer and said second metal layer and a second via layer to provide connection between said second metal layer and said third metal layer,

wherein at least each of said first metal and said third metal layers consists of a repeating pattern, and wherein at least one of said first via, second via and second metal layers comprises a custom pattern designed to customize the integrated circuit device to a specific user'"'"'s needs, wherein said third metal layer repeating pattern comprises strips extending generally in parallel to a first axis, wherein at least two vias of second via layer are underlying at least one of said strips connecting said strips to second metal layer, and wherein said at least two vias are in propinquity to a beginning and an end of said at least one of said strips.

12. A device according to claim 11 and wherein said strips are in a band of generally equal length strips.

13. A section of an integrated circuit device according to claim 11, and further comprising:

at least first and second programmable logic cells; and

at least one permanent electrical conductive path interconnecting said at least first and second programmable logic cells for customizing said device to a specific user'"'"'s needs.

14. A section of an integrated circuit device according to claim 11, and further comprising:

a logic cell array including a multiplicity of logic cells, wherein said logic cell comprises at least one look-up table.

15. A section of an integrated circuit device comprising the device according to claim 11, and further comprising:

a logic cell array including a multiplicity of logic cells, wherein said logic cell comprises at least one flip-flop.

16. A section of an integrated circuit device according to claim 13, and wherein said custom pattern is prepared with direct write e-beam lithography.

17. A section of an integrated circuit device according to claim 14, and wherein said custom pattern is prepared with direct write e-beam lithography.

18. A section of an integrated circuit device according to claim 15, and wherein said custom pattern is prepared with direct write e-beam lithography.

19. A semiconductor device comprising:

a substrate;

at least first, second and third metal layers are formed over said substrate, said second metal layer comprising a plurality of generally parallel spaced band structures extending parallel to a first axis, each band structure comprising a multiplicity of second metal layer strips extending perpendicular to said first axis;

at least one via connecting at least one second metal layer strip with said first metal layer underlying said second metal layer; and

at least one custom layer for customizing the device to a user'"'"'s specific needs.

20. A semiconductor device according to claim 19, and wherein at least one of said first via, second via, first metal and third metal layers comprises a custom pattern, and wherein said custom pattern is prepared using direct write e-beam lithography.

21. A semiconductor device according to claim 19 and wherein said third metal layer comprises:

at least one third metal layer strip extending generally perpendicular to said second metal layer strips and being connected thereto by a via.

22. A semiconductor device according to claim 19 and wherein said third metal layer comprises at least one third metal layer strip extending generally parallel to said second metal layer strips and connecting two coaxial second metal layer strips by vias.

23. A semiconductor device according to claim 19 and wherein said first metal layer comprises at least one first metal layer strip extending generally perpendicular to said second metal layer strips and being connected thereto by a via.

24. A semiconductor device according to claim 21 and also comprising at least one third metal layer strip extending parallel to said second metal layer strip and connecting two coaxial second metal layer strips.

25. A semiconductor device according to claim 19 and wherein said at least one via comprises a repeating pattern of vias.

26. A semiconductor device according to claim 19 and further comprising relatively short second metal layer strips extending parallel to said first axis and located between said band structures.

27. A semiconductor device according to claim 26 and further comprising at least one third metal layer strip extending parallel to said second metal layer strips and connecting two coaxial second metal layer strips.

28. A semiconductor device according to claim 19 and also comprising a custom via layer connecting at least one of said second metal layer strips to said third metal layer.

29. A semiconductor device according to claim 19 and wherein said third metal layer is a custom layer.

30. A section of a semiconductor device comprising the device according to claim 19, and further comprising:

at least first and second programmable logic cells; and

at least one permanent electrical conductive path interconnecting said at least first and second programmable logic cells for customizing said device to a specific user'"'"'s needs.

31. A section of a semiconductor device comprising the device according to claim 19, and further comprising:

a logic cell array including a multiplicity of logic cells, wherein said logic cell comprises at least one look-up table.

32. A section of a semiconductor device comprising the device according to claim 19, and further comprising:

a logic cell array including a multiplicity of logic cells, wherein said logic cell comprises at least one flip-flop.

33. A section of a semiconductor device according to claim 30, further comprising a custom via layer prepared with direct write e-beam lithography.

34. A section of a semiconductor device according to claim 31, further comprising a custom via layer prepared with direct write e-beam lithography.

35. A section of a semiconductor device according to claim 32, further comprising a custom via layer prepared with direct write e-beam lithography.

36. A semiconductor device comprising:

a substrate;

at least first, second and third metal layers formed over said substrate, said first metal layer comprising a plurality of generally parallel spaced band structures extending parallel to a first axis, each band structure comprising a multiplicity of first metal layer strips extending perpendicular to said first axis;

at least one via connecting at least one third metal layer strip with said second metal layer underlying said third metal layer; and

at least one custom layer for customizing the device to a user'"'"'s specific needs.

37. A semiconductor device according to claim 36, and wherein at least one of said first via, second via, second metal and third metal layers comprises a custom pattern, and wherein said custom pattern is prepared using direct write-beam lithography.

38. A semiconductor device according to claim 36 and wherein said second metal layer comprises:

at least one second metal layer strip extending generally perpendicular to said first metal layer strips and being connected thereto by a via.

39. A semiconductor device according to claim 36 and wherein said second metal layer comprises at least one second metal layer strip extending generally parallel to said first metal layer strips and connecting two coaxial first metal layer strips by vias.

40. A semiconductor device according to claim 36 and wherein said third metal layer comprises at least one third metal layer strip extending generally parallel to said first metal layer strips and having conductive path thereto.

41. A semiconductor device according to claim 38 and also comprising at least one second metal layer strip extending parallel to said first metal layer strips and connecting two coaxial first metal layer strips.

42. A semiconductor device according to claim 36 and wherein said at least one via comprises a repeating pattern of vias.

43. A semiconductor device according to claim 36 and further comprising relatively short first metal strips extending parallel to said first axis and located between said band structures.

44. A semiconductor device according to claim 43 and further comprising at least one second metal layer strip extending parallel to said first metal layer strips and connecting two coaxial first metal layer strips.

45. A semiconductor device according to claim 36 and also comprising a custom via layer connecting at least one of said first metal layer strips to said second metal layer.

46. A semiconductor device according to claim 36 and wherein said second metal layer is a custom layer.