Direct power-to-ground ESD protection with an electrostatic common-discharge line

• US 6,756,834 B1
• Filed: 04/29/2003
• Issued: 06/29/2004
• Est. Priority Date: 04/29/2003
• Status: Active Grant

• Current Assignee: Diodes Incorporated
• Original Assignee: Pericom Semiconductor Corporation (Diodes Incorporated)
• Inventors: Tong, Paul C. F., Xu, Ping Ping, Chen, Wensong, Liu, Zhi Qing, Wong, Siu-Weng Simon
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US10/249,670
• Time in Patent Office: 427 Days
• Field of Search: 327/309, 327/310, 327/313, 327/314, 327/318, 327/319, 327/320, 327/324, 327/327, 327/328, 361/90, 361/91.1, 361/91.5, 361/111
• US Class Current: 327/309
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0292 using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30

Abstract

ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O'"'"'s through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.

Claims

1. An electro-static-discharge (ESD) protected integrated circuit comprising:

first core circuitry connected between a first power bus connected to a first power pad and a first ground bus connected to a first ground pad;

second circuitry connected between a second power bus connected to a second power pad and a second ground bus connected to a second ground pad;

a common-discharge line that is not directly connected to power or ground;

a plurality of indirect ESD-protection devices coupled to the common-discharge line, each indirect ESD-protection device coupled to conduct ESD current between a pad and the common-discharge line; and

a first direct ESD clamp between the first power bus and the first ground bus, for bypassing the common-discharge line and directly conducting ESD current from the first power bus to the first ground bus when an ESD pulse is applied between the first power pad and the first ground pad, whereby ESD current is conducted through two of the plurality of indirect ESD-protection devices and the common-discharge line, or bypassing the common-discharge line through the first direct ESD clamp.

2. The ESD protected integrated circuit of claim 1 wherein the plurality of indirect ESD-protection devices include gate-coupled ESD devices that each comprise:

a conducting transistor for conducting current between the pad and the common-discharge line in response to a transistor gate; and

a coupling capacitor coupled between the pad and the transistor gate;

wherein the conducting transistor is activated to conduct ESD current from the pad to the common-discharge line when the coupling capacitor couples a portion of a voltage rise from the ESD pulse applied to the pad to the transistor gate.

3. The ESD protected integrated circuit of claim 2 wherein the conducting transistor is an n-channel transistor.

4. The ESD protected integrated circuit of claim 3 wherein the gate-coupled ESD devices each further comprise:

a local p-tap for connecting a p-well or p-substrate under the conducting transistor to a local ground,

wherein the local p-tap is connected to the local ground and not to the common-discharge line to avoid noise coupling through the common-discharge line.

5. The ESD protected integrated circuit of claim 4 wherein the gate-coupled ESD devices each further comprise:

a discharge resistor between the transistor gate and the common-discharge line.

6. The ESD protected integrated circuit of claim 1 further comprising:

a second direct ESD clamp between the second power bus and the second ground bus, for bypassing the common-discharge line and directly conducting ESD current from the second power bus to the second ground bus when an ESD pulse is applied between the second power pad and the second ground pad.

7. The ESD protected integrated circuit of claim 6 wherein the first direct ESD clamp comprises:

a direct transistor coupled to conduct ESD current between the first power bus and the first ground bus in response to a direct-transistor gate;

a direct coupling capacitor coupled between the first power bus and the direct-transistor gate.

8. The ESD protected integrated circuit of claim 7 wherein the direct transistor is an n-channel transistor.

9. The ESD protected integrated circuit of claim 8 wherein the first direct ESD clamp further comprises:

a direct discharge resistor between the direct-transistor gate and the first ground bus.

10. The ESD protected integrated circuit of claim 2 wherein the plurality of indirect ESD-protection devices further comprises an active-clamp ESD device that comprises:

an active conducting transistor for conducting current between the pad and the common-discharge line in response to an active-transistor gate;

an active coupling capacitor coupled between the common-discharge line and an inverter gate node;

an inverter between the inverter gate node and the active-transistor gate.

11. The ESD protected integrated circuit of claim 10 wherein the active-clamp ESD device further comprises:

an active resistor between the inverter gate and the pad, for discharging the active coupling capacitor.

12. The ESD protected integrated circuit of claim 1 wherein the plurality of indirect ESD-protection devices further comprises a substrate-triggered ESD device that comprises:

an substrate-triggered transistor for conducting current between the pad and the common-discharge line in response to a substrate node;

a gate resistor coupled between a gate of the substrate-triggered transistor and the common-discharge line;

a substrate-coupling capacitor coupled between the pad and the substrate node;

a substrate-discharge resistor coupled between the substrate node and the common-discharge line.

13. An electro-static-discharge (ESD) protection circuit comprising:

a common-discharge line;

a plurality of external signal pads;

a first power pad and a second power pad;

a first ground pad and a second ground pad;

a first direct power-ground clamp that comprises;

a direct capacitor connected between the first power pad and a direct-gate node;

a direct n-channel transistor having a drain connected to the first power pad,

a source connected to the first ground pad, and a gate connected to the direct-gate node;

a direct resistor for discharging the direct capacitor, the direct resistor having a terminal connected to the direct-gate node;

a plurality of protection devices coupled between the plurality of external signal pads and the common-discharge line, wherein each protection device between a protected pad and the common-discharge line comprises;

a coupling capacitor connected between the protected pad and a coupled-gate node;

a conducting n-channel transistor having a drain connected to the protected pad, a source connected to the common-discharge line, and a gate connected to the coupled-gate node;

a discharge resistor for discharging the coupling capacitor, the discharge resistor having a terminal connected to the coupled-gate node.

14. The ESD protection circuit of claim 13 further comprising:

a second direct power-ground clamp that comprises;

a second direct capacitor connected between the second power pad and a second direct-gate node;

a second direct n-channel transistor having a drain connected to the second power pad, a source connected to the second ground pad, and a gate connected to the second direct-gate node;

a second direct resistor for discharging the second direct capacitor, the second direct resistor having a terminal connected to the second direct-gate node.

15. The ESD protection circuit of claim 14 wherein the conducting n-channel transistor in each protection device has a p-tap that connects a p-type substrate under the conducting n-channel transistor to a local ground that is isolated from the common-discharge line.

16. The ESD protection circuit of claim 15 wherein the direct resistor in each protection device has a second terminal connected to the common-discharge line,

whereby the direct resistor discharges to the common-discharge line.

17. An integrated circuit comprising:

common-discharge line means for discharging electro-static-discharges between pads of the integrated circuit;

a plurality of input/output I/O pads;

a first power pad and a second power pad;

a first ground pad and a second ground pad;

first active-clamp means, between the first power pad and the common-discharge line means, for conducting electro-static-discharges from the first power pad to the common-discharge line means;

second active-clamp means, between the second power pad and the common-discharge line means, for conducting electro-static-discharges from the second power pad to the common-discharge line means;

first gate-coupled device means, between a first I/O pad in the plurality of I/O pads and the common-discharge line means, for conducting electro-static-discharges from the first I/O pad to the common-discharge line means;

second gate-coupled device means, between a second I/O pad in the plurality of I/O pads and the common-discharge line means, for conducting electro-static-discharges from the second I/O pad to the common-discharge line means;

third gate-coupled device means, between a third I/O pad in the plurality of I/O pads and the common-discharge line means, for conducting electro-static-discharges from the third I/O pad to the common-discharge line means;

first ground gate-coupled device means, between the first ground pad and the common-discharge line means, for conducting electro-static-discharges between the first ground pad to the common-discharge line means;

second ground gate-coupled device means, between the second ground pad and the common-discharge line means, for conducting electro-static-discharges between the second ground pad to the common-discharge line means.

18. The integrated circuit of claim 17 wherein the first, second, and third gate-coupled device means each comprise a gate-coupled device between an I/O pad and the common-discharge line means that comprises:

capacitor means, between the I/O pad and a gate node, for charging the gate node when an electro-static-discharge is applied to the I/O pad;

transistor means, responsive to the gate node, for conducting the electro-static-discharge from the I/O pad to the common-discharge line means;

discharge means, coupled to the gate node, for gradually discharging the capacitor means after the electro-static-discharge is conducted by the transistor means.

19. The integrated circuit of claim 18 wherein the first, second, and third gate-coupled device means each comprise the gate-coupled device between an I/O pad and the common-discharge line means that further comprises:

p-tap means, coupled to a local ground, for grounding a substrate under the transistor means.

20. The integrated circuit of claim 19 wherein the first and second active-clamp means each comprise a clamp between a power pad and the common-discharge line means that comprises:

inverter means, between an inverter node and a active-gate node, for inverting a signal on the inverter node to drive the active-gate node;

active capacitor means, between the power pad and the active-gate node, for coupling the common-discharge line means to the inverter node when an electro-static-discharge is conducted to the common-discharge line means;

active transistor means, responsive to the active-gate node, for conducting the electro-static-discharge from the power pad to the common-discharge line means;

discharge means, coupled to the inverter node, for gradually discharging the active capacitor means after the electro-static-discharge is conducted by the active transistor means.