Multiplex bus interface system and method for transmitting and receiving power and data

• US 6,756,881 B2
• Filed: 12/07/2000
• Issued: 06/29/2004
• Est. Priority Date: 12/08/1999
• Status: Active Grant

• Current Assignee: Energy Solutions (UK) Ltd.
• Original Assignee: ED&D, Inc.
• Inventors: Bush, Matthew, Bateman, David E.
• Primary Examiner(s): TWEEL JR, JOHN ALEXANDER
• Application Number:
  US09/731,952
• Publication Number:
  US 20010024441A1
• Time in Patent Office: 1,300 Days
• Field of Search: 340/310.01, 340/310.06, 340/310.02, 340/825.72, 340/825.59, 307/9.1, 307/10.1
• US Class Current: 370/212
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 2203/5458 Monitor sensor; Alarm systems
• CPC Class Codes: H04B 2203/547 via DC power distribution
• CPC Class Codes: H04B 3/548 the power on the line being DC arrangements for feeding power H04L12/10; extracting feeding power from signals H04L25/02

Abstract

A multiplex bus interface enables power and data to be transmitted and received on a two wire bus. Input and output devices operate with transceivers connected to the bus to communicate with each other by placing their data on the bus within specific time slots controlled by a controller, a clock module which broadcasts data to all connected transceivers. A pulsed power waveform provides power to the transceivers and data through pulse width modulation of the pulsed waveform. Data from the transceivers is transmitted during a time slot between power pulses. Data integrity is checked by the initiating input transceiver. Errors are reported at the end of a broadcast cycle. Output transceivers use the data as appropriate for the device and condition being monitored or controlled.

Claims

1. A communications and control system comprising:

a bus having a signal conductor;

a transceiver electrically connected to the bus for transmitting and receiving an electrical signal through the signal conductor;

a controller operable with the bus for controlling power and data delivered thereto, the controller controlling power to the transceiver through the signal conductor as a pulsed waveform having a plurality of power pulses separated by a time slot, wherein power is delivered with each voltage or power pulse and absent during the time slot for transmitting data pulses therein, the controller providing control data signals to the signal conductor and thus to the transceiver through a pulse width modulation of the pulsed waveform, and wherein a first pulse width of the power pulse represents a first data value and a second pulse width of the power pulse represents a second data value, wherein the transceiver provides data to the signal conductor of the bus within the time slot as a logical bit, and thus to the controller for full duplex operation with bi-directional communication between the controller and the transceiver, data signals being transmitted through the one signal conductor of the bus through which the power is delivered.

2. A system according to claim 1, wherein the time slot forms a preselected fixed time period between each power pulse.

3. A system according to claim 1, further comprising a computer for programming at least one of the controller and the transceiver and monitoring the data transmitted and received thereby.

4. A system according to claim 1, wherein the transceiver comprises a plurality of transceivers.

5. A system according to claim 1, wherein the transceiver comprises:

a processor operable with an input/output device for providing an electrical signal indicative of a condition communicated to and received from the input/output device;

a current transmitting circuit responsive to the electrical signal for providing a current source for the logical bit; and

a storage capacitor for distributing power to the processor and to the current transmitter circuit.

6. A system according to claim 1, wherein the controller comprises a power switch including a first semiconductor switch operable for enabling power to the bus, and a second semiconductor switch operable for controlling a time width of the power pulse forming the voltage waveform.

7. A system according to claim 1, wherein the logical bit formed within the time slot comprises a pulse width signal voltage having at least one of a first width representing a logical one and a second width representing a logical zero.

8. A system according to claim 1, wherein the conductor comprises a wire.

9. A communications and control system comprising:

a transceiver for transmitting and receiving an electrical signal; and

a controller operable with the transceiver for controlling power and data delivered thereto and controlling power to the transceiver through a pulsed waveform having a plurality of power pulses separated by a time slot, wherein power is delivered with each voltage or power pulse and absent during the time slot for transmitting data pulses therein, the controller providing control data signals to the transceiver through a pulse width modulation of the pulsed waveform, and wherein a first pulse width of the power pulse represents a first data value and a second pulse width of the power pulse represents a second data value, the transceiver providing data output within the time slot as a logical bit, and thus full duplex operation with bi-directional communication between the controller and the transceiver.

10. A system according to claim 9, further comprising a bus having a single signal conductor operable between the transceiver and the controller for the transmitting and the receiving of the electrical signal and power.

11. A system according to claim 10, wherein the conductor comprises a wire.

12. A system according to claim 9, wherein the time slot forms a preselected fixed time period between each power pulse.

13. A system according to claim 9, further comprising a computer for programming at least one of the controller and the transceiver and monitoring the data transmitted and received thereby.

14. A system according to claim 9, wherein the transceiver comprises a plurality of transceivers.

15. A system according to claim 9, wherein the transceiver comprises:

a processor operable with an input/output device for providing an electrical signal indicating a condition communicated to and received from the input/output device;

a current transmitting circuit responsive to the electrical signal for providing a current source for the logical bit; and

a storage capacitor for distributing power to the processor and to the current transmitter circuit.

16. A system according to claim 9, wherein the controller comprises a power switch including a first semiconductor switch operable for enabling power to the bus, and a second semiconductor switch operable for controlling a time width of the power pulse forming the voltage waveform.

17. A system according to claim 9, wherein the logical bit formed within the time slot comprises a pulse width signal voltage having at least one of a first width representing a logical one and a second width representing a logical zero.

18. A communications and control method comprising:

transmitting and receiving of power and data through one signal conductor, the method employing a transceiver electrically connected to the one signal conductor, a controller operating with the signal conductor for controlling power and data delivered thereto, the controller controlling power to the transceiver through the signal conductor as a pulsed waveform having a plurality of power pulses separated by a time slot, delivering the power with each power pulse and transmitting data pulses during the time slot when the power pulse is absent;

pulse width modulating the pulsed waveform for providing control data signals to the signal conductor and thus to the transceiver;

providing data to the signal conductor within the time slot as a logical bit for full duplex operation with bi-directional communication between the controller and the transceiver, data signals being transmitted through the one signal conductor through which the power is delivered.

19. A method according to claim 18, wherein a first pulse width of the power pulse represents a first data value and a second pulse width of the power pulse represents a second data value.

20. A method according to claim 18, further comprising forming a preselected fixed time period for the time slot between each power pulse.

21. A method according to claim 18, further comprising programming a computer for operation with at least one of the controller and the transceiver, and monitoring the data transmitted and received thereby.

22. A method according to claim 18, further comprising inputting and outputting an electrical signal from an input/output device operable with the transceiver.

23. A method according to claim 18, wherein the transmitting of data during the time slot comprises forming the logical bit as a pulse width signal voltage having at least one of a first width representing a logical one and a second width representing a logical zero.

24. A method according to claim 18, further comprising comparing the width of the power pulse to the width of the time slot, wherein a power pulse width equal to the time slot width represents a first logical bit value, and the power pulse width not equal to the time slot width represents a second logical bit value.