Circuit and method for DC offset calibration and signal processing apparatus using the same

• US 6,756,924 B2
• Filed: 05/16/2003
• Issued: 06/29/2004
• Est. Priority Date: 05/16/2002
• Status: Expired due to Fees

• Current Assignee: Integran Technologies Incorporated (Analog Devices, Inc.)
• Original Assignee: Integran Technologies Incorporated (Analog Devices, Inc.)
• Inventors: Lee, Junghwan, Kim, Bo-Eun, Jeong, Minsu, Kim, Bonkee, Lim, Jinkyu
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US10/438,941
• Publication Number:
  US 20030214423A1
• Time in Patent Office: 410 Days
• Field of Search: 341/120, 341/118, 341/122, 330/9, 330/2, 455/255, 455/63
• US Class Current: 341/120
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 3/45995 using switching means

Abstract

A signal processing apparatus for correcting DC offset in a communication system is provided. The signal processing apparatus comprises: a low noise amplifier (LNA) 301; a mixer 303 for mixing the output from said LNA 301 with local oscillation signal LO; a first offset correction amplifier 305 for amplifying output signal from said mixer 303 and for eliminating DC offset in the output signal in accordance with first control signal Vc31; a second offset correction amplifier 309 for amplifying output signal from said first offset correction amplifier 305 and for eliminating DC offset in the output signal in accordance with second control signal Vc32; a variable gain amplifier 311 for amplifying output from said second offset correction amplifier 309 wherein gain is controlled such that power level of output be maintained to a desired value; offset calibration mean 313 for calibrating DC offset in output from said variable gain amplifier 311; and offset correction mean 315 for outputting the first and second control signals Vc31 and Vc32 in accordance with the output from said offset calibration mean 313, to eliminate DC offset in the output from said variable gain amplifier 311.

Claims

1. Signal processing apparatus comprising:

a low noise amplifier (LNA) 301;

a mixer 303 for mixing the output from said LNA 301 with local oscillation signal LO;

a first offset correction amplifier 305 for amplifying output signal from said mixer 303 and for eliminating DC offset in the output signal in accordance with first control signal Vc31;

a second offset correction amplifier 309 for amplifying output signal from said first offset correction amplifier 305 and for eliminating DC offset in the output signal in accordance with second control signal Vc32;

a variable gain amplifier 311 for amplifying output from said second offset correction amplifier 309 wherein gain is controlled such that power level of output be maintained to a desired value;

offset calibration mean 313 for calibrating DC offset in output from said variable gain amplifier 311; and

offset correction mean 315 for outputting the first and second control signals Vc31 and Vc32 in accordance with the output from said offset calibration mean 313, to eliminate DC offset in the output from said variable gain amplifier 311.

2. The signal processing apparatus of claim 1, wherein

said first and second offset correction amplifiers comprises respectively:

a differential amplifier 5100 for receiving an input signal differentially, amplifying the received input signal, and outputting amplified signal through first and second output terminals 505 and 507;

a first correction unit 5300 for eliminating DC offset appearing in outputs from the first and second output terminals 505 and 507 of said differential amplifier 5100; and

a second correction unit 5500 connected between said first and second output terminals 505 and 507 of said differential amplifier 5100 and said first correction unit 5300, for eliminating offset in the output from said first and second output terminals 505 and 507 of said differential amplifier 5100.

3. The signal processing apparatus of claim 2,

wherein said differential amplifier 5100 comprises first and second NMOS transistors MN71 and MN72, drains of said first and second NMOS transistors MN71 and MN72 form the first and second output terminals 505 and 507, respectively, gates form the first and second input terminals 501 and 503, respectively, and sources are connected to each other.

4. The signal processing apparatus of claim 2,

wherein said first correction unit 5300 comprises first and second variable resistors R71 and R72, which are connected between voltage source VDD and the first and second output terminals 505 and 507 of said differential amplifier 5100, respectively.

5. The signal processing apparatus of claim 4,

wherein first variable resistor R71 is formed by first variable current source I81 and first resistor R81 which are connected in parallel and second variable resistor R72 is formed by second variable current source I82 and second resistor R82 which are connected in parallel.

6. The signal processing apparatus of claim 2,

wherein said second correction unit comprises:

a first MOS transistor MN73 having a gate connected to the first output terminal 505, a drain connected to the voltage source, and a source,

a second MOS transistor MN74 having a gate connected to the second output terminal 507, a drain connected to the voltage source, and a source, and

first and second variable current sources each supplying currents to each sources of the first and second MOS transistors MN73 and MN74 varying in accordance with the first and second control signals I71 and I72, respectively.

7. The signal processing apparatus of claim 1,

wherein said offset correction mean 315 comprises a control unit 317 and a register 319, and

said control unit 317 controls data recorded in the register 319 in accordance with the output from said offset calibration mean 313.

8. The signal processing apparatus of claim 1 further comprising:

a filter for filtering output from said first offset correction amplifier 305 to output desired signal to said second offset correction amplifier 309.

9. The signal processing apparatus of claim 8,

wherein cutoff frequency and degree of said filter is programmable.

10. The signal processing apparatus of claim 1,

wherein said offset calibration mean 313 comprises a comparator 313 for comparing the differential output signals of said variable gain amplifier 311.

11. The signal processing apparatus of claim 10,

wherein said offset calibration mean 313 further comprises a counter connected to the output of the comparator for evaluating sampling values of the comparator'"'"'s output and, outputs an average of the results.

12. The signal processing apparatus of claim 10,

wherein said offset calibration mean 313 further comprises a filter 401 connected between the outputs of said variable gain amplifiers 311a and 311b and said comparator 403 for attenuating A.C. signal.

13. The signal processing apparatus of claim 1,

wherein if said variable gain amplifier 311 comprises multi-stage amplifiers, said offset calibration mean calibrates DC offset from output of one of the amplifier stage in said multi-stage amplifiers just before the final amplifier stage in said multi-stage amplifiers.

14. The signal processing apparatus of claim 1 further comprising:

a switching mean connected between said second offset correction amplifier 309 and said offset correction mean 315.

15. The signal processing apparatus of claim 7,

wherein said register 319 is a successive approximation register (SAR) type.

16. The signal processing apparatus of claim 1,

wherein said offset correction mean 315 comprises a sensing unit for sensing variation data in register which controls either frequency of LO or cut-off frequency of filter 307.

17. The signal processing apparatus of claim 7,

wherein said offset correction mean 315 further comprises an up-down counter for increasing or decreasing value in said register 319.

18. Signal processing apparatus comprising:

a LNA 331;

a mixer 333 for mixing the output from said LNA 331 with local oscillation signal LO;

a first variable gain amplifier 337 for amplifying output from said LNA 331 while controlling the gain thereof;

means connected to output of said first variable gain amplifier 337 for eliminating DC components in the output from said first variable gain amplifier 337;

an offset correction amplifier 339 for amplifying output from said means for eliminating DC offset in the output in accordance with a first control signal;

a second variable gain amplifier 341 for amplifying output from said offset correction amplifier 339 while controlling the gain thereof;

offset calibration mean 343 for calibrating DC offset in output from said second variable gain amplifier 341; and

offset correction mean 345 for outputting the control signal in accordance with output from said offset calibration mean 343, to eliminate DC offset in the output from said variable gain amplifier 341.

19. The signal processing apparatus of claim 18,

wherein said means for eliminating DC components in the output from said first variable gain amplifier 337 comprises a capacitor.

20. Signal processing apparatus comprising:

an offset correction amplifier for amplifying signals received to first and second input terminal differentially to output through first and second output terminals, respectively, and for eliminating DC offset in the received signals in accordance with a offset control signal;

a variable gain amplifier for amplifying output of said offset correction amplifier while controlling gain thereof;

offset calibration means for calibrating DC offset in output from said variable gain amplifier; and

offset correction means for outputting the offset control signal for correcting DC offset calibrated by said offset calibration means.

21. Method for correcting DC offset in a signal processing apparatus comprising steps of:

activating the signal processing apparatus;

setting initial data for correcting DC offset;

sensing whether either frequency of PLL or cutoff frequency of LPF is changed;

correcting DC offset, when a change is sensed in the sensing step, and determining the correction data from MSBs to LSBs n a successive approximation method; and

correcting DC offset, when a change is not sensed in the sensing step or the correcting step is completed, by calibrating DC offset in a real time base and increasing or decreasing the correction data pursuant to the calibrated DC offset.

22. Method for correcting DC offset in a signal processing apparatus comprising steps of:

activating the signal processing apparatus;

setting initial data for correcting DC offset;

correcting DC offset and determining the correction data from MSBs to LSBs n a successive approximation method; and

correcting DC offset by calibrating DC offset in a real time base and increasing or decreasing the correction data pursuant to the calibrated DC offset.