Method and apparatus for interleaving read and write accesses to a frame buffer

• US 6,756,987 B2
• Filed: 04/20/2001
• Issued: 06/29/2004
• Est. Priority Date: 04/20/2001
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Goyins, Gregg S., McVey, John R.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/839,856
• Publication Number:
  US 20020154129A1
• Time in Patent Office: 1,166 Days
• Field of Search: 345/540, 345/539, 345/531, 345/545, 345/550, 345/501, 711/157, 711/170, 711/5, 711/100, 711/154, 711/167, 711/168
• US Class Current: 345/540
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

Some embodiments of a data channel that interleaves read and write access to a frame buffer include a bit-plane storage device, a single frame buffer, a data controller and a digital pixel display. Transferring data through the single frame buffer by interleaving reads and writes includes (1) alternately writing to the frame buffer and reading from the frame buffer portions of each bit-plane of a sequence bit-plane data; and (2) writing to said frame buffer so as to replace each said portion of a bit-plane in the frame buffer with a corresponding portion of a next bit-plane. By interleaving read and write accesses, a single frame buffer and less interface logic are necessary to transfer data from a storage device to a digital pixel display. In a three channel digital color pixel imaging device, this reduces the number of frame buffer SDRAM units from six to three, and significantly reduces the overall cost associated with implementing data flow through the data storage and frame buffer blocks.

Claims

1. A method for transferring bit-plane data to and from a frame buffer, said method interleaving write and read accesses to said frame buffer, said method comprising:

alternately writing to said frame buffer and reading from said frame buffer at least two portions of each bit-plane of said bit-plane data; and

writing to said frame buffer so as to replace each of said portions of each bit-plane in said frame buffer with a corresponding portion of a next bit-plane.

2. The method as claimed in claim 1, wherein said frame buffer comprises a data storage array that is divided into at least two data banks, each data bank capable of storing a corresponding one of said at least two portions of each bit-plane.

3. The method as claimed in claim 2, wherein each of said at least two portions of a bit-plane is read from one of said at least two data banks to a corresponding one of at least two pixel banks of a digital pixel display.

4. The method as claimed in claim 1, wherein prior to said alternately writing a portion of said data to and reading a portion of said data from said frame buffer, the method further comprises:

receiving one of a digital pixel image and an analog image;

upon receiving an analog image, converting said analog image into a digital pixel image;

image processing said digital pixel image;

gamma correcting said digital pixel image;

remapping said digital pixel image into an ordered sequence of bit-planes; and

storing said ordered sequence of bit-planes in a storage device.

5. An apparatus for transferring data to and from a frame buffer, said apparatus comprising:

a storage device storing digital pixel image data as a sequence of bit-planes;

a frame buffer capable of storing one of said bit-planes;

a digital pixel display that includes an array of pixel sites corresponding to an array of single-bits comprising each of said bit-planes;

circuitry that controls data transfer from said storage device to said frame buffer and from said frame buffer to said digital pixel display; and

a first program code to transfer said data by interleaving read and write accesses to said frame buffer, said program code comprising;

alternately writing to said frame buffer and reading from said frame buffer at least two portions of each bit-plane of said bit-plane data; and

writing to said frame buffer so as to replace each of said portions of each bit-plane in said frame buffer with a corresponding portion of a next bit-plane.

6. The apparatus as claimed in claim 5, wherein said frame buffer comprises a data storage array that is divided into at least two data banks, each data bank capable of storing a corresponding one of said at least two portions of each bit-plane.

7. The apparatus as claimed in claim 6, wherein each of said at least two portions of a bit-plane is read from one of said at least two data banks to a corresponding one of at least two pixel banks of the digital pixel display.

8. The apparatus as claimed in claim 5, further comprising:

a device to at least one of receive a digital pixel image, and receive an analog image and convert said analog image into a digital pixel image;

a device to process said digital pixel image;

a device to gamma correct said digital pixel image; and

a device to remap said digital pixel image into an ordered sequence of bit-planes.

9. A method for transferring data to and from a frame buffer, said method interleaving write and read accesses to said frame buffer, said method comprising:

alternately writing a portion of said data to said frame buffer and reading a portion of said data from said frame buffer; and

after writing a portion of said data to each data bank in said frame buffer, writing each subsequent portion of said data to said frame buffer so as to replace a portion of said data in said frame buffer that had been previously read from said frame buffer, wherein said data includes at least one sequence of bit-planes and said frame buffer includes a data storage array corresponding to an array of single-bit data that comprises each of said bit-planes.

10. The method as claimed in claim 9, wherein each of said bit-planes comprises at least two bit-plane data sets, said data storage array comprises at least two corresponding data banks, and each portion of said data stored in said frame buffer comprises one of said bit-plane data sets and is stored in one of said data banks.

11. The method as claimed in claim 10, wherein said interleaving read and write accesses to said frame buffer further comprises:

a) writing a first bit-plane from a storage device to said frame buffer;

b) reading a first data set from a first data bank of said frame buffer to a digital pixel display;

c) writing a first data set from a second bit-plane in said storage device to said first data bank of said frame buffer;

d) alternately reading data sets from other data banks of said frame buffer and writing corresponding second bit-plane data sets to said other banks of said frame buffer until all data sets from said second bit-plane have been written from said storage device into said frame buffer; and

e) repeating procedures b), c) and d) for writing third and subsequent bit-planes to said frame buffer.

12. The method as claimed in claim 9, wherein prior to said alternately writing a portion of said data to and reading a portion of said data from said frame buffer the method further comprises:

receiving one of a digital pixel image and an analog image;

upon receiving an analog image, converting said analog image into a digital pixel image;

image processing said digital pixel image;

gamma correcting said digital pixel image;

remapping said digital pixel image into an ordered sequence of bit-planes; and

storing said ordered sequence of bit-planes in a storage device.

13. An apparatus for transferring data to and from a frame buffer, said apparatus comprising:

said data stored in a storage device;

a frame buffer;

a digital pixel display;

circuitry that controls data transfer from said storage device to said frame buffer and from said frame buffer to said digital pixel display; and

a first program code to transfer said data by interleaving read and write accesses to said frame buffer, said program code comprising;

alternately writing a portion of said data to said frame buffer and reading a portion of said data from said frame buffer; and

after reading a first portion of said data from said frame buffer, writing each said a portion of said data so as to replace a portion of said data in said frame buffer that had been previously read from said frame buffer, wherein said data includes at least one sequence of bit-planes and said frame buffer includes a data storage array corresponding to an array of single-bit data that comprises each of said bit-planes.

14. The apparatus as claimed in claim 13, wherein each of said bit-planes comprises at least two bit-plane data sets, said data storage array comprises at least two corresponding data banks, and each portion of said data stored in said frame buffer comprises one of said bit-plane data sets and is stored in one of said data banks.

15. The apparatus as claimed in claim 14, wherein said program for interleaving read and write accesses to said frame buffer further comprises:

a) writing a first bit-plane from a storage device to said frame buffer;

b) reading a data set from a first data bank of said frame buffer to a digital pixel display;

c) writing a first data set from a second bit-plane in said storage device to said first data bank of said frame buffer;

d) alternately reading data sets from other data banks of said frame buffer and writing corresponding second bit-plane data sets to said other banks of said frame buffer until all data sets from said second bit-plane have been written from said storage device into said frame buffer; and

e) repeating procedures b), c) and d) for writing third and subsequent bit-planes to said buffer.

16. The apparatus as claimed in claim 13, further comprising:

a device to at least one of receive a digital pixel image, and receive an analog image data and convert said analog image into a digital pixel image;

a device to process said digital pixel image;

a device to gamma correct said digital pixel image; and

a device to remap said digital pixel image into an ordered sequence of bit-planes.

17. The apparatus as claimed in claim 13, wherein said apparatus further comprises:

circuitry that controls data transfer to said digital pixel display through at least two data channels; and

at least two frame buffers, one frame buffer connected to each of said at least two data channels.

18. The apparatus as claimed in claim 17, wherein said apparatus further comprises:

a digital color imaging device that receives single-bit pixel data for three color bands through three data channels;

circuitry that controls data transfer to said imaging device through three data channels; and

three frame buffers, one frame buffer connected to each of said three data channels.

19. A method for transferring data to and from a frame buffer, said method alternately writing a portion of said data to and reading a portion of said data from said frame buffer, wherein each said reading a portion of said data comprises reading a different portion of data than that written to said frame buffer during the immediately prior said writing a portion of said data, wherein said data includes at least one sequence of bit-planes and said frame buffer includes a data storage array corresponding to an array of single-bit data that comprises each of said bit-planes.

20. The method as claimed in claim 19, wherein each of said bit-planes comprises at least two bit-plane data sets, said data storage array comprises at least two corresponding data banks, and each portion of said data stored in said frame buffer comprises one of said bit-plane data sets and is stored in one of said data banks.

21. The method as claimed in claim 19, wherein prior to said alternately writing a portion of said data to and reading a portion of said data from said frame buffer the method further comprises:

receiving one of digital pixel image and an analog image;

upon receiving an analog image, converting said analog image into a digital pixel image;

image processing said digital pixel image;

gamma correcting said digital pixel image;

remapping said digital pixel image into an ordered sequence of bit-planes; and

storing said ordered sequence of bit-planes in a storage device.

22. An apparatus for transferring data to and from a frame buffer, said apparatus comprising:

data stored in a storage device;

a frame buffer;

a digital pixel display;

circuitry that controls data transfer from said storage device to said frame buffer and from said frame buffer to said digital pixel display; and

a first program code to transfer said data by alternately writing a portion of said data to and reading a portion of said data from said frame buffer, wherein each said reading a portion of said data comprises reading a different portion of data than that written to said frame buffer during the immediately prior said writing a portion of said data, wherein said data includes at least one sequence of bit-planes and said frame buffer includes a data storage array corresponding to an array of single-bit data that comprises each of said bit-planes.

23. The apparatus as claimed in claim 22, wherein each of said bit-planes comprises at least two bit-plane data sets, said data storage array comprises at least two corresponding data banks, and each portion of said data stored in said frame buffer comprises one of said bit-plane data sets and is stored in one of said data banks.

24. The apparatus as claimed in claim 22, further comprising:

a device to at least one of receive a digital pixel image, and receive an analog image and convert said analog image into a digital pixel image;

a device to process said digital pixel image;

a device to gamma correct said digital pixel image; and

a device to remap said digital pixel image into an ordered sequence of bit-planes.