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Low-power parallel processor and imager having peripheral control circuitry

  • US 6,757,019 B1
  • Filed: 03/10/2000
  • Issued: 06/29/2004
  • Est. Priority Date: 03/13/1999
  • Status: Expired due to Fees
First Claim
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1. An apparatus for detecting an image at a predetermined resolution comprising:

  • an integrated circuit chip including;

    an image sensor array, said image sensor array capable of detecting said image at the predetermined resolution and outputting detected signals corresponding to said sensed image at said predetermined resolution;

    a plurality of processor elements each coupled to said image sensor array and capable of inputting a predetermined number of said detected signals, such that each of said detected signals are input to one of said plurality of processor elements, said processor elements each concurrently operating upon said input detected signals using video-image algorithmic coding, and generating encoded signals corresponding thereto, said encoded signals being concurrently output from each of said plurality of parallel processor elements;

    an output comparator for translating the encoded signals output from the parallel processor elements and generating information representative of the encoded signals;

    an array processor memory for controlling operation of the plurality of processor elements; and

    a main controller, operable in parallel with the array processor, for performing control monitoring of the array processor and the parallel processor elements.

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