Low-power parallel processor and imager having peripheral control circuitry

• US 6,757,019 B1
• Filed: 03/10/2000
• Issued: 06/29/2004
• Est. Priority Date: 03/13/1999
• Status: Expired due to Fees

• Current Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Original Assignee: Board of Trustees of the Leland Stanford Junior University (Stanford University)
• Inventors: Hsieh, Jeff Y. F., Meng, Teresa H. Y.
• Primary Examiner(s): MOE, AUNG SOE
• Application Number:
  US09/523,584
• Time in Patent Office: 1,572 Days
• Field of Search: 348/308, 348/302, 348/306, 348/294, 250/208.1
• US Class Current: 348/302
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

The present invention implements a parallel processing architecture in which a plurality of parallel processors concurrently operate upon a different block, preferably a column, of image data. Implemented on a single monolithic integrated circuit chip, this single chip solution has characteristics that provide the throughput necessary to perform computationally complex operations, such as color correction, RGB to YUV conversion and DCT operations in either still or video applications, and motion estimation in digital video processing applications. Particular uses of the invention in systems processing image data according to an MPEG2 image compression technique and according to a digital video (DV) image compression technique are disclosed.

Claims

1. An apparatus for detecting an image at a predetermined resolution comprising:

an integrated circuit chip including;

an image sensor array, said image sensor array capable of detecting said image at the predetermined resolution and outputting detected signals corresponding to said sensed image at said predetermined resolution;

a plurality of processor elements each coupled to said image sensor array and capable of inputting a predetermined number of said detected signals, such that each of said detected signals are input to one of said plurality of processor elements, said processor elements each concurrently operating upon said input detected signals using video-image algorithmic coding, and generating encoded signals corresponding thereto, said encoded signals being concurrently output from each of said plurality of parallel processor elements;

an output comparator for translating the encoded signals output from the parallel processor elements and generating information representative of the encoded signals;

an array processor memory for controlling operation of the plurality of processor elements; and

a main controller, operable in parallel with the array processor, for performing control monitoring of the array processor and the parallel processor elements.

2. The apparatus of claim 1, wherein the main controller is further for post-processing the information generated by the output comparator.

3. The apparatus of claim 1, wherein the array processor controller is for controlling the processor elements by simple branching and pipelining of instructions.

4. The apparatus of claim 1, wherein the array processor controller is for controlling the processor elements using data-independent branches.

5. The apparatus of claim 1, wherein the main controller is for controlling starting and stopping of the array processor controller.

6. The apparatus of claim 1, wherein the main controller and the array processor controller synchronize with one another through the exchange of processing synchronization information.

7. The apparatus of claim 1, wherein the output comparator is for generating the information based on a reordering of the signals output by the processor elements.

8. The apparatus of claim 1, wherein the information generated by the output comparator includes information reflective of the status of a processor element.

9. The apparatus of claim 1, where the output comparator is for buffering information exchanged between the processor elements and the main controller.

10. The apparatus of claim 1, wherein the output comparator is for selecting a set of processor elements to execute a pipelined instruction stream and causing processor elements not in the set to ignore the stream.

11. The apparatus of claim 1, wherein the information generated by the output comparator includes status information reflective of the collective status of all processor elements.

12. The apparatus of claim 1, wherein the output comparator is for providing information directly from the main controller to a selected group of processor elements.

13. The apparatus of claim 1, wherein the output comparator is for providing information representative of the status of program completion of a processor element to the array processor controller.

14. The apparatus of claim 1, wherein the output comparator is for providing information representative of the execution by a processor element of a processing milestone.

15. An apparatus for detecting an image at a predetermined resolution comprising:

an integrated circuit chip including

an image sensor array, the image sensor array capable of detecting the image at the predetermined resolution and outputting detected signals corresponding to the sensed image at the predetermined resolution;

a plurality of instruction-programmable processor elements each coupled to the image sensor array and capable of inputting a predetermined number of the detected signals, such that each of the detected signals are input to one of the plurality of instruction-programmable processor elements, the instruction-programmable processor elements each concurrently operating upon the input detected signals using video-image algorithmic coding, and generating encoded signals corresponding thereto, the encoded signals being concurrently output from each of the plurality of parallel instruction-programmable processor elements;

an output comparator for translating the encoded signals output from the parallel instruction-programmable processor elements and generating information representative of the encoded signals;

an array processor memory for controlling operation of the plurality of instruction-programmable processor elements; and

a main controller, operable in parallel with the array processor, for performing control monitoring of the array processor and the parallel instruction-programmable processor elements.