Coding method of multi-level memory cell

• US 6,757,193 B2
• Filed: 04/03/2002
• Issued: 06/29/2004
• Est. Priority Date: 05/31/2001
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Liu, Cheng-Jye, Chen, Chia-Hsing
• Primary Examiner(s): Yoha, Connie C.
• Application Number:
  US10/115,799
• Publication Number:
  US 20020181278A1
• Time in Patent Office: 818 Days
• Field of Search: 365/185.03, 365/185.09, 365/185.24, 365/185.33, 365/185.04
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A coding method of a multi-level cell, applied to a programming operation of a multi-level memory cell. The multi-level memory cell can store n bits and has 2ⁿ levels with respect to 2ⁿ codes. Each code is constructed with n bits. In the coding method, a code to be stored is provided. According to a relationship between the code and level, the multi-level memory cell has a specified level for corresponding code to be stored. The relationship is a correspondence between the 2ⁿ codes and the 2ⁿ levels. Two codes corresponding to any neighboring two levels has only a one-bit difference.

Claims

1. A coding method multi-level memory cell, applied to a multi-level memory cell, wherein the multi-level memory has a storage capacity of n bits and has 2ⁿ codes of 2ⁿ levels, wherein each code comprises n bits, the coding method comprising:

providing a code to be stored, wherein the code to be stored belongs to one of the 2ⁿ codes; and

obtaining a specified level corresponding to the code to be stored for the multi-level memory cell according to a relationship between the 2ⁿ code and the 2ⁿ level;

wherein;

the specified level belongs to one of the 2ⁿ levels; and

two codes of any two neighboring two levels have an one bit difference, wherein a size for storing error code corrections is reduced.

2. The coding method according to claim 1, wherein 2≦

n≦

4.

3. The coding method according to claim 1, wherein n=2, and a number of the levels is 4.

4. The coding method according to claim 3, wherein the levels comprise a first to a fourth levels from high to low, and a code corresponding to the first level is (00), (01), (10) or (11).

5. The coding method according to claim 3, wherein the levels comprise a first to a fourth levels from high to low, and codes corresponding to the first to the fourth levels include (01), (11), (10), (00).

6. The coding method according to claim 1, wherein n=3, and a number of the levels is 8.

7. The coding method according to claim 6, wherein the levels comprise a first to a eighth levels from high to low, and a code corresponding to the first level is (000), (001), (010), (011), (100), (101), (110) or (111).

8. The coding method according to claim 6, wherein the levels comprise a first to an eighth levels from low to high, and codes corresponding to the first to the eighth levels include (000), (001), (011), (010), (110), (111), (101), (100).

9. The coding method according to claim 1, wherein the multi-level memory cell includes a flash electrically erasable programmable read only memory (flash EEPROM) cell.

10. The coding method according to claim 1, wherein the multi-level memory cell includes a flash erasable programmable read only memory (flash EPROM) cell.

11. The coding method according to claim 1, wherein the multi-level memory cell includes an erasable programmable read only memory (EPROM) cell.

12. The coding method according to claim 1, wherein the multi-level memory cell includes a mask read only memory (Mask ROM) cell.

13. The coding method according to claim 1, wherein the multi-level memory cell includes a dynamic random access memory (DRAM) cell.

14. A coding method multi-level memory cell, applied to a multi-level memory cell having a storage capacity of n bits and having 2ⁿ codes of 2ⁿ levels, wherein each code comprises n bits, the coding method comprising:

providing a predetermined code, wherein the code to be stored belongs to one of the 2ⁿ codes; and

obtaining a predetermined level corresponding to the code to be stored for the multi-level memory cell according to a relationship between the 2ⁿ code and the 2ⁿ level;

wherein;

the predetermined level belongs to one of the 2ⁿ levels, and two codes of any two neighboring two levels have an one bit difference, wherein a size for storing error code corrections is reduced; and

an actual stored code of the multi-level memory cell is checked to compare a difference between predetermined code and the actual stored code, and when a specified bit difference exists between the predetermined code and the actual stored code, an address of the multi-level memory cell and the specified bit are recorded.

15. A programming method of a multi-level memory, applied to a multi-level memory comprising a plurality of multi-level memory cells and a plurality of error code correction memory cells, wherein each of the multi-memory cell has a storage capacity of n bits and has 2ⁿ codes corresponding to 2ⁿ levels, and wherein each of the codes comprises n bits, the programming method comprising:

providing a plurality of predetermined codes covered in the 2ⁿ codes;

storing the predetermined codes in the multi-level memory, wherein each multi-level memory cell has a specified level according to a relationship of code-level, and the relationship of code-level is a relationship between the 2ⁿ codes and the 2ⁿ levels, and two codes of any two neighboring levels have an one-bit difference, wherein a size for storing error code corrections is reduced; and

checking a plurality of actual codes stored in the multi-level memory cells, wherein each actual code is compared to each of the predetermined codes, and when a specified bit difference is checked between any of the predetermined codes and any of the actual stored codes, an address of any of the multi-level cells and the specified code are recorded in the error code correction memory cells.

16. The programming method according to claim 15, wherein the multi-level memory cells comprise 2^q bits, the error code correction memory cells comprise 2q−

1 bits, and q is an integer.

17. The programming method according to claim 16, wherein q=9.