Synchronous flash memory command sequence
First Claim
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1. A synchronous flash memory device comprising:
- an array of non-volatile memory cells; and
a command register to store command data used to control flash memory operations, wherein the command register is coupled to receive the command data through memory address connections during an internal flash operating mode, wherein the internal flash operating mode is initiated using a predetermined sequence of ACTIVE, WRITE, and/or READ commands.
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Abstract
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous flash memory device, in one embodiment, has a command interface comprising a writer enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal. A command operation is initiated in response to a sequence of ACTIVE/WRITE and/or ACTIVE/READ commands provided on the WE#, CAS# and RAS# connections.
36 Citations
21 Claims
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1. A synchronous flash memory device comprising:
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an array of non-volatile memory cells; and
a command register to store command data used to control flash memory operations, wherein the command register is coupled to receive the command data through memory address connections during an internal flash operating mode, wherein the internal flash operating mode is initiated using a predetermined sequence of ACTIVE, WRITE, and/or READ commands. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A synchronous flash memory device comprising:
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an array of non-volatile memory cells arranged in addressable blocks;
external address connections to receive externally provided address data;
a mode register to store mode data used to set a mode of the synchronous flash memory device; and
a command register to store command data used to control flash memory operations, wherein the command register is coupled to receive the command data through memory address connections during an internal flash operating mode, wherein the internal flash operating mode is initiated using a sequence comprising ACTIVE, WRITE, and/or READ commands. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A synchronous flash memory device comprising:
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an array of non-volatile memory cells; and
a control circuit to initiate a command operation in response to a predefined sequence of externally provided ACTIVE, WRITE, and/or READ commands. - View Dependent Claims (14)
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15. A synchronous data system comprising:
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a memory controller; and
a synchronous flash memory device coupled to the memory controller and comprising, an array of non-volatile memory cells, and a control circuit to initiate a command operation in response to a predefined sequence of externally provided ACTIVE, WRITE, and/or READ commands from the memory controller. - View Dependent Claims (16)
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17. A method of loading commands in a synchronous flash memory, the method comprising:
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initiating a command register load operation using a predefined combination of ACTIVE, WRITE, and/or READ commands, wherein the ACTIVE commands are defined as a high column address strobe (CAS#) signal, a low row address strobe (RAS#) signal, and a high write enable (WE#) signal , and the WRITE commands are defined as a low column address strobe (CAS#) signal, a high row address strobe (RAS#) signal, and a low write enable (WE#) signal; and
loading command information into the command register using address connections of the synchronous flash memory in response to the command register load operation. - View Dependent Claims (18, 19, 20, 21)
placing command information on address input connections.
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19. The method of claim 17 further comprising:
placing command information on address input connections.
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20. The method of claim 17 further comprising:
performing a read operation following the initiation of the command register load operation utilizing an ACTIVE command and a READ command.
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21. The method of claim 17 further comprising:
performing a program operation following the initiation of the command register load operation utilizing an ACTIVE command and a WRITE command.
Specification