Method and apparatus for output rate regulation and control associated with a packet pipeline
First Claim
1. An apparatus, comprising:
- a pipeline having a series of stages, where, a first of said pipeline stages has a first interface for coupling to a memory that stores a pointer to output flow information for a packet, said pointer obtainable from said memory via a TOS value found within said packet'"'"'s header information or assigned by a second pipeline stage that precedes said first pipeline stage, and where, another of said pipeline stages has;
(i) a second interface to receive packet size information of said packet, (ii) a third interface to receive token bucket information for said output flow, (iii) shaping logic coupled to said second and third interfaces, and (iv) an output from said shaping logic, said output to provide a delay for said packet that is consistent with said output flow, where said second pipeline stage follows said first pipeline stage.
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Accused Products
Abstract
An apparatus having a pipeline having a series of stages. At least one of the pipeline stages has a first interface for coupling to a memory that stores output capacity information for a packet. The output capacity information is obtainable from the packet'"'"'s packet header information or internal information where the internal information is used within a service provider'"'"'s network. At least one of the pipeline stages has a second interface that receives packet size information; a third interface that receives the output capacity information; and comparison logic coupled to the second and third interfaces.
A method that involves presenting packet header information and packet size information to one or more pipeline stages where the packet header information and the packet size information correspond to a packet. Then, determining within a stage associated with the pipeline, with the packet header information, output capacity for the packet. Then, comparing within a stage associated with the pipeline, the output capacity with the packet size to determine appropriate delay for the packet.
115 Citations
71 Claims
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1. An apparatus, comprising:
a pipeline having a series of stages, where, a first of said pipeline stages has a first interface for coupling to a memory that stores a pointer to output flow information for a packet, said pointer obtainable from said memory via a TOS value found within said packet'"'"'s header information or assigned by a second pipeline stage that precedes said first pipeline stage, and where, another of said pipeline stages has;
(i) a second interface to receive packet size information of said packet, (ii) a third interface to receive token bucket information for said output flow, (iii) shaping logic coupled to said second and third interfaces, and (iv) an output from said shaping logic, said output to provide a delay for said packet that is consistent with said output flow, where said second pipeline stage follows said first pipeline stage.- View Dependent Claims (2, 3, 4, 5)
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6. A method, comprising:
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presenting packet header information from a second packet to a first pipeline stage and presenting packet size information and other information from which delay can be calculated for a first packet to a second pipeline stage;
retrieving a pointer to output flow information for said second packet with said first pipeline stage and calculating an appropriate output delay for said first packet with said second pipeline stage;
presenting packet size information and other information from which delay can be calculated for said second packet to said second pipeline stage and queuing a packet identifier into an output packet organizer at a location that corresponds to said delay for said first packet with a third pipeline stage, where, said packet identifier identifies where said first packet can be found in a packet buffer. - View Dependent Claims (7, 8, 9, 10)
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11. An apparatus for regulating traffic offered by a network to a first user of said network and a second user of said network, said apparatus comprising:
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a) a first pipeline stage having a data bus to receive a first output flow identifier, where, said first output flow identifier points to a first memory location where parameters for a first output flow are located, where said first output flow is for a first packet that is to be sent from a packet buffer to said first user, and where, said first output flow is characterized at least by a first output rate; and
b) a second pipeline stage having shaping logic circuitry coupled to register storage space, said register storage space to provide to said shaping logic circuitry at least one characteristic of said first output rate, said second pipeline stage to;
(i) determine a delay for said first packet that conforms to said first output rate, (ii) during a same pipeline cycle in which;
said first pipeline stage receives upon said data bus a second output flow identifier that points to a second memory location where parameters for a second output flow are located, where, said second output flow is for a second packet that is to be sent from said packet buffer to said second user, and where, said second output flow is characterized at least by a second output rate. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
(i) places;
a first packet identifier into a location within an output packet organizer, said output packet organizer having different locations that correspond to different waiting times for said first packet within said packet buffer, said location within said output packet organizer corresponding to said delay, said first packet identifier identifying where said first packet can be found within said buffer memory (ii) during a same pipeline cycle in which;
said second pipeline stage determines a delay for said second packet that conforms to said second output rate.
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34. A method for regulating traffic offered by a network to a first user of said network and a second user of said network, said method comprising:
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a. retrieving in response to a first packet that is to be sent from a packet buffer to said first user, a first output flow identifier that points to a first memory location where a first output flow is located, said first output flow having a first output rate and a first priority; and
,b. determining a location within an output packet organizer, said output packet organizer having different locations that correspond to different waiting times for said first packet within said packet buffer, said determined location within said output packet organizer corresponding to a waiting time for said first packet that conforms to said first output rate and said first priority, during a same pipeline cycle in which;
a second output flow identifier that points to a second memory location where a second output flow is located is retrieved, said second output flow having a second output rate and a second priority, said retrieving of said second output flow in response to a second packet that is to be sent from said packet buffer to said second user. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55)
(i) placing;
a first packet identifier into said determined location within said output packet organizer, said first packet identifier identifying where said first packet can be found within said buffer memory (ii) during a same pipeline cycle in which;
a second location within said output packet organizer is determined, said second location corresponding to a waiting time for said second packet that conforms to said second output rate and said second priority.
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56. An apparatus for regulating traffic offered by a network to a first user of said network and a second user of said network, said apparatus comprising:
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a) a first pipeline stage comprising;
1) a first data bus to receive from a first memory;
(i) during a first pipeline cycle;
a first output flow identifier;
(ii) during a second pipeline cycle;
a second output flow identifier; and
b) a second pipeline stage that follows said first pipeline stage, said second pipeline stage comprising;
1) a second data bus to receive from a second memory;
(i) during said second pipeline cycle and from a location of said second memory pointed to by said first output flow identifier;
a first TOS parameter for a first output packet, said first output packet destined for said first user;
(ii) during a third pipeline cycle and from a location of said second memory pointed to by said second output flow identifier;
a second TOS parameter for a second output packet, said second output packet destined for said second user;
2) register space in which to store;
(i) during said second pipeline cycle;
a first parameter from which a first delay for said first packet that is consistent with said first output flow can be calculated;
(ii) during said third pipeline cycle;
a second parameter from which a second delay for said second packet that is consistent with said second output flow can be calculated;
3) logic circuitry to calculate;
(i) during said second pipeline cycle;
said first delay;
(ii) during said third pipeline cycle;
said second delay. - View Dependent Claims (57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68)
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69. A machine readable medium containing a description of a semiconductor circuit design for regulating traffic offered by a network to a first user of said network and a second user of said network, said description comprising a description of:
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a) a first pipeline stage having a data bus to receive a first output flow identifier, where, said first output flow identifier points to a first memory location where parameters for a first output flow are located, where said first output flow is for a first packet that is to be sent from a packet buffer to said first user, and where, said first output flow is characterized at least by a first output rate; and
b) a second pipeline stage having shaping logic circuitry coupled to register storage space, said register storage space to provide to said shaping logic circuitry at least one characteristic of said first output rate, said second pipeline stage to;
(i) determine a delay for said first packet that conforms to said first output rate, (ii) during a same pipeline cycle in which said first pipeline stage receives upon said data bus a second output flow identifier that points to a second memory location where parameters for a second output flow are located, where, said second output flow is for a second packet that is to be sent from said packet buffer to said second user, and where, said second output flow is characterized at least by a second output rate. - View Dependent Claims (70, 71)
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Specification