Method and apparatus for data communication and storage wherein a IEEE1394/firewire clock is synchronized to an ATM network clock

• US 6,757,304 B1
• Filed: 01/26/2000
• Issued: 06/29/2004
• Est. Priority Date: 01/27/1999
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Maruyama, Atsushi, Nomura, Takashi
• Primary Examiner(s): VINCENT, DAVID ROBERT
• Application Number:
  US09/491,280
• Time in Patent Office: 1,616 Days
• Field of Search: 370/402, 370/419, 370/438, 370/458, 370/489, 370/498, 370/395.1, 370/395.61, 370/395.62, 370/503-4, 370/509-14, 370/516, 370/520, 710/100, 710/107-8, 710/126, 386/66, 386/71, 386/84, 386/85
• US Class Current: 370/516
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04L 12/40058 Isochronous transmission
• CPC Class Codes: H04L 12/40097 Interconnection with other networks LAN interconnection over a bridge based backbone H04L12/462; single bridge functionality H04L12/462
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/5674 Synchronisation, timing recovery or alignment
• CPC Class Codes: H04N 5/765 Interface circuits between an apparatus for recording and another apparatus

Abstract

The present invention relates to a data communication system for data communication between a bus and a network. This data communication system of the present invention includes a first interface device for performing interface processing for the bus, a second interface device for performing interface processing for the network, and a generating device for generating a first clock used by the first interface device in synchronization with a second clock used for causing processes in the network to be synchronized.

Claims

1. A data communication system for data communication between a serial bus and an ATM (Asynchronous Transfer Mode) network, the data communication system comprising:

first interface means for performing interface processing for said bus;

second interface means for performing interface processing for said network; and

generating means for generating a first clock used by said first interface means as a cycle master clock for said bus in synchronization with a second clock used as a reference clock for said ATM network;

whereby said first clock is generated by a phase locked loop wherein the phase of a frequency-divided version of said first clock is compared to the phase of said second clock and the frequency of said first clock is adjusted according to the result of the phase comparison.

2. A data communication system according to claim 1, wherein:

said bus is an IEEE1394 serial bus.

3. A data communication system according to claim 1, further comprising:

control means for controlling said first interface means and said second interface means; and

frequency-dividing means for generating an interrupt control signal provided to said control means by performing frequency-division on said second clock.

4. A data communication method for data communication between a serial bus and an ATM (Asynchronous Transfer Mode network, the data communication method comprising:

a first interfacing step for performing interface processing for said bus;

a second interfacing step for performing interface processing for said network; and

a generating step for generating a first clock used by said first interfacing step as a cycle master clock for said bus in synchronization with a second clock used as a reference clock for said ATM network;

whereby said first clock is generated by a phase locked loop wherein the phase of a frequency-divided version of said first clock is compared to the phase of said second clock and the frequency of said first clock is adjusted according to the result of the phase comparison.

5. A data communication system for data communication between a serial bus and an ATM (Asynchronous Transfer Mode) network, the data communication system comprising:

first interface means for performing interface processing for said serial bus;

second interface means for performing interface processing for said network; and

generating means for generating a first clock used by said first interface means as a cycle master clock for said bus in synchronization with a second clock used as a reference clock for said ATM network;

whereby said first clock is generated by a phase locked loop wherein the phase of a frequency-divided version of said first clock is compared to the phase of said second clock and the frequency of said first clock is adjusted according to the result of the phase comparison; and

whereby the frequency of said first clock is based on a frame timing signal used by said network.

6. A data communication method for data communication between a serial bus and an ATM (Asynchronous Transfer Mode) network, the data communication method comprising:

a first interfacing step for performing interface processing for said serial bus;

a second interfacing step for performing interface processing for said network; and

a generating step for generating a first clock used by said first interfacing step as a cycle master clock for said bus in synchronization with a second clock used as a reference clock for said ATM network;

whereby said first clock is generated by a phase locked loop wherein the phase of a frequency-divided version of said first clock is compared to the phase of said second clock and the frequency of said first clock is adjusted according to the result of the phase comparison; and

whereby the frequency of said first clock is based on a frame timing signal used by said network.

7. A data communication system for transmitting data from a transmitting unit to a receiving unit via a first serial bus, an ATM (Asynchronous Transfer Mode) network, and a second serial bus, the data communication system comprising:

first interface means for performing interface processing for said first serial bus;

second interface means for performing interface processing for said network;

third interface means for performing interface processing for said second serial bus; and

generating means for generating a first clock used by said third interface means as a cycle master clock for said second bus in synchronization with a second clock used by said second interface means as a reference clock for said ATM network, whereby said first clock is generated by a phase locked loop wherein the phase of a frequency-divided version of said first clock is compared to the phase of said second clock and the frequency of said first clock is adjusted according to the result of the phase comparison; and

whereby a reference clock of said first serial bus and said first clock are synchronized.

8. A data communication method for transmitting data from a transmitting unit to a receiving unit via a first serial bus, an ATM (Asynchronous Transfer Mode) network, and a second serial bus, the data communication method comprising:

a first interfacing step for performing interface processing for said first serial bus;

a second interfacing step for performing interface processing for said network;

a third interfacing step for performing interface processing for said second serial bus; and

a generating step for generating a first clock used by said third interface means as a cycle master clock for said second bus in synchronization with a second clock used by said second interface means as a reference clock for said ATM network, whereby said first clock is generated by a phase locked loop wherein the phase of a frequency-divided version of said first clock is compared to the phase of said second clock and the frequency of said first clock is adjusted according to the result of the phase comparison; and

whereby a reference clock of said first serial bus and said first clock are synchronized.

9. A computer-readable storage medium containing a program to perform processing by a data communication method for data communication between a serial bus and an ATM (Asynchronous Transfer Mode network, the data communication method comprising:

a first interfacing step for performing interface processing for said bus;

a second interfacing step for performing interface processing for said network; and

a generating step for generating a first clock used by said first interfacing step as a cycle master clock for said bus in synchronization with a second clock used as a reference clock for said ATM network;

whereby said first clock is generated by a phase locked loop wherein the phase of a frequency-divided version of said first clock is compared to the phase of said second clock and the frequency of said first clock is adjusted according to the result of the phase comparison.