Universal serial bus interfacing using FIFO buffers

• US 6,757,763 B1
• Filed: 04/07/2000
• Issued: 06/29/2004
• Est. Priority Date: 04/07/2000
• Status: Expired due to Term

• Current Assignee: Lantiq Beteiligungs-GmbH & Company KG (Intel Corporation)
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG)
• Inventors: Preiss, Frank, Staudt, Christian, Hartung, Joerg
• Primary Examiner(s): Lefkowitz, Sumati
• Assistant Examiner(s): VU, TRISHA U
• Application Number:
  US09/545,393
• Time in Patent Office: 1,544 Days
• Field of Search: 710/36-57, 710/305-315, 710/71, 710/105, 710/106, 713/501
• US Class Current: 710/105
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

An improved Universal Serial Bus interface employing FIFO buffers (300, 800) for interfacing to an application bus and a microprocessor bus, in particular, an XBUS. The interface includes a plurality of transmit/receive channels (114) multiplexed to the application bus and the XBUS. Each transmit channel includes a transmit FIFO buffer (300), a transmit write buffer (308), a transmit push buffer (310), and three transmit state machines: a transmit write state machine (302), a transmit interrupt state machine (313), and a transmit push state machine (313). The transmit state machine (302) and the transmit FIFO (300) are clocked in the USB domain. The transmit write register (308) is clocked in the XBUS domain. Each receive channel includes a receive FIFO buffer (800), a receive state machine (802), and a receive register (806). The receive FIFO (800), the receive state machine (802), and the receive register (806) are all clocked in the USB domain.

Claims

1. A bus interface system for interfacing between a first bus and a second bus, comprising:

a transmit multiplexer coupled to the first bus;

a plurality of transmit channels multiplexed by the transmit multiplexer to transmit data to said first bus, said plurality of transmit channels each including a transmit block having at least one dedicated transmit FIFO buffer for interfacing to said first bus and at least one interface register for interfacing to said second bus;

a receive multiplexer coupled to the first bus; and

a plurality of receive channels multiplexed by the receive multiplexer to receive data from said first bus, said plurality of receive channels each including a receive block having at least one dedicated receive FIFO buffer for interfacing to said first bus and at least one interface register for interfacing to said second bus;

wherein at least one of said transmit block and receive block includes a control state machine.

2. A bus interface system in accordance with claim 1, said transmit block including at least one control state machine.

3. A bus interface system in accordance with claim 2, said control state machine in said transmit block and said transmit FIFO buffer operating on a first bus clock, and said transmit interface register operating on a second bus clock.

4. A bus interface system in accordance with claim 1, said receive block including at least one control state machine.

5. A bus interface system in accordance with claim 4, said control state machine in said receive block, said receive FIFO buffer, and said receive interface register operating on a first bus clock.

6. A bus interface system for interfacing between a first bus and a second bus, comprising:

a transmit multiplexer coupled to the first bus;

a plurality of transmit channels multiplexed by the transmit multiplexer to transmit data to said first bus, said plurality of transmit channels each including first means having at least one dedicated transmit FIFO buffer for interfacing to said first bus and at least one interface register for interfacing to said second bus;

a receive multiplexer coupled to the first bus; and

a plurality of receive channels multiplexed by the receive multiplexer to receive data from said first bus, said plurality of receive channels each including second means having at least one dedicated receive FIFO buffer for interfacing to said first bus and at least one interface register for interfacing to said second bus

wherein at least one of said first means and second means includes a control state machine.

7. A bus interface system in accordance with claim 6, said first means including at least one control state machine.

8. A bus interface system in accordance with claim 7, said control state machine in said first means and said transmit FIFO buffer operating on a first bus clock, and said transmit interface register operating on a second bus clock.

9. A bus interface system in accordance with claim 6, said second means including at least one control state machine.

10. A bus interface system in accordance with claim 9, said control state machine in said second means, said receive FIFO buffer, and said receive interface register operating on a single bus clock.