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Universal serial bus interfacing using FIFO buffers

  • US 6,757,763 B1
  • Filed: 04/07/2000
  • Issued: 06/29/2004
  • Est. Priority Date: 04/07/2000
  • Status: Expired due to Term
First Claim
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1. A bus interface system for interfacing between a first bus and a second bus, comprising:

  • a transmit multiplexer coupled to the first bus;

    a plurality of transmit channels multiplexed by the transmit multiplexer to transmit data to said first bus, said plurality of transmit channels each including a transmit block having at least one dedicated transmit FIFO buffer for interfacing to said first bus and at least one interface register for interfacing to said second bus;

    a receive multiplexer coupled to the first bus; and

    a plurality of receive channels multiplexed by the receive multiplexer to receive data from said first bus, said plurality of receive channels each including a receive block having at least one dedicated receive FIFO buffer for interfacing to said first bus and at least one interface register for interfacing to said second bus;

    wherein at least one of said transmit block and receive block includes a control state machine.

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