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Apparatus and technique for maintaining order among requests issued over an external bus of an intermediate network node

  • US 6,757,768 B1
  • Filed: 05/17/2001
  • Issued: 06/29/2004
  • Est. Priority Date: 05/17/2001
  • Status: Active Grant
First Claim
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1. An ordering circuit configured to off-load responsibility for maintaining order among requests issued over a split transaction bus from a processor to a split transaction bus controller of an intermediate network node, the ordering circuit comprising:

  • a command table having a plurality of entries, each entry adapted to track a pending read request issued by the processor and destined for the split transaction bus;

    conflict detection logic coupled to the command table, the conflict detection logic comparing an address of a write request issued by the processor with an address of a pending read request stored in each entry of the command table, the conflict detection logic asserting a conflict bit corresponding to an entry of the command table when the address of any pending read request stored in the entry matches the address of write request; and

    a read-in-progress register having a plurality of bits, each bit corresponding to a pending read request sent over the bus, wherein assertion of a bit of the read-in-progress register and the conflict bit causes the write request to wait until all pending read requests complete before being sent over the split transaction bus to thereby maintain order among read and write requests directed to the same address on the bus.

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