Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices

• US 6,757,800 B1
• Filed: 02/05/2002
• Issued: 06/29/2004
• Est. Priority Date: 07/31/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Estakhri, Petro, Iman, Berhanu
• Primary Examiner(s): MCLEAN MAYO, KIMBERLY N
• Application Number:
  US10/071,972
• Time in Patent Office: 875 Days
• Field of Search: 711/168, 711/103, 711/5, 711/202, 711/150, 365/189.04, 365/230.03, 365/210, 365/200, 365/185.11, 360/49, 360/39, 360/54, 360/31
• US Class Current: 711/168
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored. The storage system includes a memory controller coupled to the host; and a nonvolatile memory bank coupled to the memory controller via a memory bus, the memory bank being included in a nonvolatile semiconductor memory unit, the memory bank has storage blocks each of which includes a first row-portion located in said memory unit, and a corresponding second row-portion located in each of the memory unit, each of the memory row-portions provides storage space for two of said sectors, wherein the speed of performing write operations is increased by writing sector information to the memory unit simultaneously.

Claims

1. A memory storage system for storing information organized in sectors within a nonvolatile memory bank defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each said sector including a user data portion and an overhead portion, said sectors being organized into blocks, each block identified by a virtual physical block address (PBA) and including sub-blocks, each sub-block being located in a memory device, each sector identified by a host-provided logical block address (LBA) and an actual PBA, said host-provided LBA being received by said storage device from the host for identifying a sector of information to be accessed, said actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored, said storage system comprising:

a memory controller coupled to said host; and

a nonvolatile memory bank coupled to said memory controller via a memory bus, said memory bank being included in a non-volatile semiconductor memory unit, said memory bank having storage blocks including sub-blocks with corresponding sub-blocks of a block identified by the same virtual PBA and each block including a first row-portion located in said memory unit, and a corresponding second row-portion located in said memory unit, a block being assignable based upon the identification of a free location within said memory bank for storing information, each said memory row-portions providing storage space for two or more of said sectors, said sectors each for including sector information, received from the host, said received sectors being identified by sector numbers of a predetermined order, said memory controller for writing sector information, received from the host, to a first sector location of a particular sub-block of a particular block, said memory controller for further writing sector information, received from the host, to a first sector location of a sub-block of the particular block that is other than the particular sub-block,

wherein the speed of performing write operations is increased by writing a plurality of sector information to the memory device simultaneously regardless of the predetermined order of the sector numbers.

2. A memory storage system as recited in claim 1 wherein said memory controller includes:

a data buffer for temporarily storing said sector-organized information;

a microprocessor;

a space manager including a space manager controller and a space manager memory unit for maintaining a map for translating said LBA to said PBA; and

an error correction code logic unit for performing error coding and correction operations on said sector-organized information.

3. A memory storage system as recited in claim 1 wherein:

each of said first row-portions includes,

a first even sector field for storing even data bytes of an even sector, and

a first odd sector field for storing even data bytes of an odd sector;

each of said second row-portions includes,

a second even sector field for storing odd data bytes of said even sector, and

a second odd sector field for storing odd data bytes of said odd sector;

said memory bus includes,

a first split bus coupled to transmit said even data bytes of said sectors between said memory controller and said memory unit;

a second split bus coupled to transmit said odd data bytes of said sectors between said memory controller and said memory unit.

4. A memory storage system as recited in claim 3 wherein each of said second row-portions further includes:

a first error correction field for storing error correction information corresponding to said even sector;

a second error correction field for storing error correction information corresponding to said odd sector;

a block address field for storing said PBA which specifies an address of said corresponding block, and

a flag field for storing information indicative of the status of said corresponding block.

5. A memory storage system as recited in claim 4 wherein each of said first row-portions further includes:

a first error correction field for storing error correction information corresponding to said even sector;

a second error correction field for storing error correction information corresponding to said odd sector; and

a block address field for storing said PBA which specifies an address of said corresponding block, and

a flag field for storing information indicative of the status of said corresponding block.

6. A memory storage system as recited in claim 5 wherein:

each of said first and second row-portions includes storage space for 512 bytes of said user data plus an additional 16 bytes of storage space for said overhead information; and

said first split bus and said second split bus each include 8 bit lines.

7. A memory storage system as recited in claim 6 wherein said controller includes:

means for accessing an even sector of information by simultaneously accessing said first and second even sector fields of corresponding row-portions of said memory unit via said first and second split buses; and

means for accessing an old sector of information by simultaneously accessing said first and second odd sector fields of corresponding row-portions of said memory units via said first and second split buses.

8. A memory storage system as recited in claim 7 wherein said controller includes error correction code logic for performing error coding and correction operations on said sector-organized information.

9. A memory storage system as recited in claim 8 wherein said flag field is used to store block level flags including:

a used/free block flag indicating whether said corresponding block is currently being used to store information; and

a defect block flag indicating whether said corresponding block is defective.

10. A memory storage system as recited in claim 9 wherein each of said corresponding sub-blocks are identified by a single PBA value.

11. A memory storage system as recited in claim 10 wherein said non-volatile memory unit is a flash memory chip.

12. A memory storage system as recited in claim 11 wherein:

each of said first row-portions includes a first sector field for storing data bytes of a first sector;

each of said second row-portions includes a second sector field for storing data bytes of a second sector;

said memory bus includes,

a first split bus coupled to transmit the least significant data bytes of said sectors between said memory controller and said memory unit;

a second split bus coupled to transmit the most significant data bytes of said sectors between said memory controller and said memory unit.

13. A memory storage system comprising:

memory control circuitry coupled to a host for transferring therebetween sectors of information; and

a nonvolatile memory unit for storing information organized into sectors, said nonvolatile memory unit coupled to said memory control circuitry via a memory bus for receiving more than one sector of information from the host, said memory unit having blocks, each block identified by a virtual physical block address (PBA) and including sub-blocks with corresponding sub-blocks of a block identified by the same virtual PBA, a block being assignable based upon the identification of a free location within said memory bank for storing information, and each block including a plurality of rows, each row including a plurality of row-portions, each said memory row-portions providing storage space for at least one of said sectors, said sectors each for including sector information, received from the host, said received sectors being identified by sector numbers of a predetermined order, said memory controller for writing sector information, received from the host, to a first sector location of a particular sub-block of a particular block, said memory controller for further writing sector information, received from the host, to a first sector location of a sub-block of the particular block that is other than the particular sub-block

wherein the speed of performing write operations is increased by writing two or more sectors of information to one or more rows of the nonvolatile memory unit simultaneously regardless of the predetermined order of the sector numbers.

14. A memory storage system as recited in claim 13 wherein said nonvolatile memory unit includes one or more nonvolatile memory devices and wherein said rows of a block span across one or more nonvolatile memory devices.

15. A memory storage system as recited in claim 14 wherein said row-portions include a user data portion and an overhead portion.

16. A memory storage system as recited in claim 15 wherein said row of a block includes a first row-portion, and a second row-portion.

17. A memory storage system as recited in claim 16 wherein said memory control circuitry is coupled to a host for communicating command, address and data information therebetween.

18. A memory storage system as recited in claim 13 wherein said memory control circuitry includes:

a data buffer for temporarily storing said sector-organized information;

a microprocessor;

a space manager including a space manager controller and a space manager memory unit for maintaining a map for translating logical block addresses to physical block addresses; and

an error correction code logic unit for performing error coding and correction operations on said sector-organized information.

19. A memory storage system as recited in claim 16 wherein:

each of said first row-portions includes,

a first even sector field for storing even data bytes of a first sector, and

a first odd sector field for storing even data bytes of a second sector;

each of said second row-portions includes,

a second even sector field for storing odd data bytes of said first sector, and

a second odd sector field for storing odd data bytes of said second sector;

said memory bus includes,

a first split bus coupled to transfer said even data bytes of said sectors between said memory control circuitry and said memory unit;

a second split bus coupled to transfer said odd data bytes of said sectors between said memory control circuitry and said memory unit.

20. A memory storage system as recited in claim 19 wherein each of said second row-portions further includes:

a first error correction field for storing error correction information corresponding to said first sector;

a second error correction field for storing error corrections information corresponding to said second sector;

a block address field for storing a physical block address for identifying an address of said corresponding block; and

a flag field for storing information indicative of the status of said corresponding block.

21. A memory storage system as recited in claim 20 wherein each of said first row-portions further includes:

a first error correction field for storing error correction information corresponding to said first sector;

a second error correction field for storing error correction information corresponding to said second sector; and

a block address field for storing said physical block address identifying an address of said corresponding block, and

a flag field for storing information indicative of the status of said corresponding block.

22. A memory storage system as recited in claim 21 wherein:

each of said first and second row-portions includes storage space for 512 bytes of said user data plus an additional 16 bytes of storage space for said overhead information; and

said first split bus and said second split bus each include 8 bit lines.

23. A memory storage system as recited in claim 21 wherein said memory control circuitry includes:

means for accessing a first sector of information by simultaneously accessing said first and second even sector fields of corresponding row-portions of said memory unit via said first and second split buses; and

means for accessing a second sector of information by simultaneously accessing said first and second odd sector fields of corresponding row-portions of said memory units via said first and second split buses.

24. A memory storage system as recited in claim 23 wherein said memory control circuitry includes error correction code logic for performing error coding and correction operations on said sector-organized information.

25. A memory storage system as recited in claim 24 wherein said flag field including:

a used/free block flag indicating whether said corresponding block is currently being used to store information; and

a defect block flag indicating whether said corresponding block is defective.

26. A memory storage system as recited in claim 25 wherein said nonvolatile memory unit includes one or more flash memory chips.

27. A memory storage system as recited in claim 26 wherein:

said memory bus includes,

a first split bus coupled to transfer the least significant data bytes between said memory control circuitry and said memory unit; and

a second split bus coupled to transfer the most significant data bytes between said memory control circuitry and said memory unit.

28. A memory storage system comprising:

memory control circuitry; and

a nonvolatile memory unit for storing information organized into sectors, said nonvolatile memory unit coupled to said memory control circuitry via a memory bus, said memory unit having blocks, each block identified by a virtual physical block address (PBA) and including sub-blocks with corresponding sub-blocks of a block identified by the same virtual PBA, a block being assignable based upon the identification of a free location within said memory bank for storing information, and each block including a plurality of rows, each row including a plurality of row-portions, each said memory row portions providing storage space for at least one of said sectors, said sectors each for including sector information, received from the host, said received sectors being identified by sector numbers of a predetermined order, said memory controller for writing sector information, received from the host, to a first sector location of a particular sub-block of a particular block, said memory controller for further writing sector information, received from the host, to a first sector location of a sub-block of the particular block that is other than the particular sub-block

wherein the speed of performing write operations is increased by writing two or more sectors of information to one or more rows of the nonvolatile memory unit simultaneously regardless of the predetermined order of the sector numbers.

29. A memory storage system as recited in claim 28 wherein said nonvolatile memory unit includes one or more nonvolatile memory devices and wherein said rows of a block span across one or more nonvolatile memory devices.

30. A memory storage system as recited in claim 28 wherein said row-portions include a user data portion and an overhead portion.

31. A memory storage system as recited in claim 28 wherein said memory control circuitry is coupled to a host for communicating command, address and data information therebetween.

32. A memory storage system as recited in claim 28 wherein said memory control circuitry includes:

a data buffer for temporarily storing said sector-organized information;

a microprocessor;

a space manager including a space manager controller and a space manager memory unit for maintaining a map for translating logical block address to physical block address; and

an error correction code logic unit for performing error coding and correction operations on said sector-organized information.

33. A memory storage system as recited in claim 28 wherein a row of a block includes a first row-portion and a second row-portion comprising:

each of said first row-portions includes,

a first even sector field for storing even data bytes of a first sector, and

a first odd sector field for storing even data bytes of a second sector;

each of said second row-portions includes,

a second even sector field for storing odd data bytes of said first sector, and

a second odd sector field for storing odd data bytes of said second sector;

said memory bus includes,

a first split bus coupled to transfer said even data bytes of said sectors between said memory control circuitry and said memory unit;

a second split bus couple dot transfer said odd data bytes of said sectors between said memory control circuitry and said memory unit.

34. A memory storage system as recited in claim 33 wherein each of said second row-portions further includes:

a first error correction field for storing error correction information corresponding to said first sector;

a second error correction field for storing error correction information corresponding to said second sector;

a block address field for storing a physical block address for identifying an address of said corresponding block, and

a flag field for storing information indicative of the status of said corresponding block.

35. A memory storage system as recited in claim 34 wherein each of said first row-portions further includes:

a first error correction field for storing error correction information corresponding to said first sector;

a second error correction field for storing error correction information corresponding to said second sector, and

a block address field for storing said physical block address identifying an address of said corresponding block, and

a flag field or storing information indicative of the status of said corresponding block.

36. A memory storage system as recited in claim 35 wherein:

each of said first and second row-portions includes storage space for 512 bytes of said user data plus an additional 16 bytes of storage space for said overhead information; and

said first split bus and said second split bus each include 8 bit lines.

37. A memory storage system as recited in claim 35 wherein said memory control circuitry includes:

means for accessing a first sector of information by simultaneously accessing said first and second even sector fields of corresponding row-portions of said memory unit via said first and second split buses; and

means for accessing a second sector of information by simultaneously accessing said first and second odd sector field of corresponding row-portions of said memory units via said first and second split buses.

38. A memory storage system as recited in claim 37 wherein said memory control circuitry includes error correction code logic for performing error coding and correction operation on said sector-organized information.

39. A memory storage system as recited in claim 38 wherein said flag field including:

a used/free block flag indicating whether said corresponding block is currently being used to store information; and

a defect block flag whether said corresponding block is defective.

40. A memory storage system as recited in claim 39 wherein said nonvolatile memory unit includes one or more flash memory chips.

41. A memory storage system as recited in claim 28 wherein:

said memory bus includes,

a first split bus coupled to transfer the least significant data bytes between said memory control circuitry and said memory unit; and

a second split bus coupled to transfer the most significant data bytes between said memory control circuitry and said memory unit.

42. In a storage system including a nonvolatile memory unit and a controller coupled to said memory unit, a method of performing memory management comprising:

portioning the memory unit into plurality of blocks, each of which includes a plurality of rows for storing sectors, and further partitioning a row into a plurality of row-portions, each of said memory row-portions providing storage space for at least one of said sectors, a block being assignable based upon the identification of a free location within said memory bank for storing information, said sectors each for including sector information, received from the host, said received sectors being identified by sector numbers of a predetermined order, said memory controller for writing sector information, received from the host, to a first sector location of a particular sub-block of a particular block, said memory controller for further writing sector information, received from the host, to a first sector location of a sub-block of the particular block that is other than the particular sub-block,

wherein the speed of performing write operations is increased by writing two or more sector information to two or more of the nonvolatile memory unit simultaneously regardless of the predetermined order of the sector numbers.

43. In a storage system as recited in claim 42, the method further comprising defining a first row-portion and a second row-portion within a row of a block, providing a first sector having a first data byte and a second data byte and providing a second sector having a first data byte and a second data byte.

44. A memory storage system for storing information organized into sectors within a nonvolatile memory unit having one or more memory banks defined by sector storage locations, said memory banks being organized into one or more blocks having one or more sectors, each sector identified by host-provided logical block address (LBA) and actual physical block address (PBA), said host-provided LBA being received from the host for identifying a sector information to be accessed, said actual PBA developed by said storage system within said each memory bank wherein said sector is to be stored, said storage system comprising:

memory control circuitry; and

a nonvolatile memory unit having one or more memory banks having storage blocks, each of which providing storage space for storing two or more sectors, a block being assignable based upon the identification of a free location within said memory bank for storing information, said sectors each for including sector information, received from the host, said received sectors being identified by sector numbers of a predetermined order, said memory controller for writing sector information, received from the host, to a first sector location of a particular sub-block of a particular block, said memory controller for further writing sector information, received from the host, to a first sector location of a sub-block of the particular block that is other than the particular sub-block,

wherein programming a plurality of sector information into one or more memory banks within a nonvolatile memory unit simultaneously regardless of the predetermined order of the sector numbers increases the speed of performing program operation.

45. A memory storage system for storing information organized into sectors within a nonvolatile memory unit having one or more memory banks defined by sector storage locations, each sector including a user data portion and an overhead portion, said sectors being organized into blocks within each memory bank, each sector identified by host-provided logical block address (LBA) and actual physical block address (PBA), said host-provided LBA being received by the memory storage system from a host for identifying a sector information to be accessed, said actual PBA developed by said storage system within said each memory bank wherein said one or more sectors received from the host is to be stored, said storage system comprising:

a. a data buffer for temporarily storing data received from the host;

b. control unit for receiving one or more sectors from the host into said data buffer; and

c. a nonvolatile semiconductor memory unit having one or more memory banks having storage blocks, each of which providing storage space for storing two or more sectors, a block being assignable based upon the identification of a free location within said memory bank for storing information, said sectors each for including sector information, received from the host, said received sectors being identified by sector numbers of a predetermined order, said memory controller for writing sector information, received from the host, to a first sector location of a particular sub-block of a particular block, said memory controller for further writing sector information, received from the host, to a first sector location of a sub-block of the particular block that is other than the particular sub-block,

wherein the speed of performing program operation is increased by programming two or more sectors from a data buffer to multiple memory banks simultaneously regardless of the predetermined order of the sector numbers within a nonvolatile memory device.

46. A memory storage system for storing information organized into sectors within a nonvolatile memory unit, said sectors being organized into blocks, each sector identified by a host-provided logical block address (LBA) and an actual physical block address (PBA), said host-provided LBA being received by said memory storage system from a host for identifying a sector of information to be accessed, said actual PBA developed by said memory storage system to identify where within said nonvolatile memory unit said sector is to be stored, said storage system comprising:

memory control circuitry; and

a nonvolatile memory unit having one or more memory locations, each of said memory locations providing storage space for storing two or more sectors, a block being assignable based upon the identification of a free location within said memory bank for storing information, said sectors each for including sector information, received from the host, said received sectors being identified by sector numbers of a predetermined order, said memory controller for writing sector information, received from the host, to a first sector location of a particular sub-block of a particular block, said memory controller for further writing sector information, received from the host, to a first sector location of a sub-block of the particular block that is other than the particular sub-block

wherein programming a plurality of sector information to one or more memory locations within a nonvolatile memory unit simultaneously regardless of the predetermined order of the sector numbers, increases the speed of performing program operation.