Logic block used to check instruction buffer configuration

• US 6,757,831 B1
• Filed: 08/18/1999
• Issued: 06/29/2004
• Est. Priority Date: 08/18/1999
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Folmsbee, Alan
• Primary Examiner(s): Peeso, Thomas R.
• Application Number:
  US09/377,344
• Time in Patent Office: 1,777 Days
• Field of Search: 713/190, 713/193, 713/194, 713/200, 713/201
• US Class Current: 713/190
• CPC Class Codes: G06F 21/123 by using dedicated hardware, e.g. dongles, smart cards, cryptographic processors, global positioning systems [GPS] devices
• CPC Class Codes: G06F 21/14 against software analysis or reverse engineering, e.g. by obfuscation
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU with its operation modified. In order to execute program instructions, the buffer interdependencies must match that expected by the compiler. This makes analysis of the program operation extremely difficult. The instruction buffer on a keyed microprocessor contains logic which is able to route a subset of the instruction bits on the microprocessor. This selects destination logic gates in the microprocessor which eventually reach a programmable instruction decoder and an instruction buffer interdependency checking logic block.

Claims

1. A particularly configurable microprocessor for processing computer programs which are selectively operable on said particularly configurable microprocessor, comprising:

a store for key shared with a compiler, the key used by the compiler to encrypt standard instructions into encrypted instructions;

an instruction buffer which contains logic circuitry for routing a subset of the instruction bits from bit locations in the buffer to destination logic circuitry; and

an instruction buffer interdependency checking logic block responsive to said routing of the instruction bits, wherein the key stored in more than one memory cell type including a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only”

Memory (E²PROM), and a Random Access Memory (RAM);

the key including bits expandable into a larger set of bits which control the instruction decoder, signal routing, and logic gate reconfiguration;

a serial number in ROM which participates in the allocation of logic gates and routing of signals, and communicated to the compiler to inform the compiler of custom allocation and routing; and

the key providing a capability of controlling signal routing, and logic gate reconfiguration whether the instructions are encrypted instructions or standard instructions.

2. The microprocessor of claim 1, wherein:

the logic circuitry includes reconfigurable logic gates, said reconfigurable logic gates calculating the results of execution of an instruction;

the logic gates calculate the results of the execution of an instruction and makes provisions for accepting correct data operands and plausible wrong data operands; and

the logic gates calculate the results of the execution of an instruction include provisions for outputting correct results along with plausible wrong results.

3. The microprocessor of claim 2, wherein:

at least a portion of the reconfigurable logic gates calculate the results of the execution of an instruction;

said portion of the logic gates includes provisions for accepting correct data operands and plausible wrong data operands; and

said portion of the logic gates includes provisions for outputting correct results along with plausible wrong results.

4. The microprocessor of claim 1, wherein:

the key includes the error correction key, and including instruction key information shared with a compiler, the instruction key information used by the compiler to encrypt standard instructions into encrypted instructions; and

the key and the encrypted instructions coordinate variations of data numeric representations.

5. The microprocessor of claim 1, wherein a choice is provided of using encrypted instructions or standard instructions.

6. The microprocessor of claim 1, further comprising:

logic gates configured to process data coded in various numeric representations and the logic gates able to accept results of the instruction execution using various

numeric representations;

logic gates configured to immediately process said coded data; and

the data representation able to change several times during the execution of a program so that numeric encodings of input data operands and output data results can vary.

7. The microprocessor of claim 1, wherein:

the key includes the error correction key, and including instruction key information shared with a compiler, the instruction key information used by the compiler to encrypt standard instructions into encrypted instructions; and

data and instructions are provided to a computer via program information include an intentional introduction of errors which are correctable with error correction algorithms, said correction algorithms pre-selected according to the key.

8. The microprocessor of claim 7, wherein said correction algorithms are pre-selected according to long instruction words and changed on a periodic basis by codes provided in the instructions gathered into the instruction buffer.

9. A particularly configurable microprocessor for processing computer programs which are selectively operable on said particularly configurable microprocessor, comprising:

a store for key shared with a compiler, the key used by the compiler to encrypt standard instructions into encrypted instructions,

an instruction buffer which contains logic circuitry for routing a subset of the instruction bits from bit locations in the buffer to destination logic circuitry

an instruction buffer interdependency checking logic block responsive to said routing of the instruction bits, and

an output register for data results able to contain both correct results and plausible wrong results, the results in word locations in the output register coordinated by the key.

10. A particularly configurable microprocessor for processing computer programs which are selectively operable on said particularly configurable microprocessor, comprising:

a store for key shared with a compiler, the key used by the compiler to encrypt standard instructions into encrypted instructions;

an instruction buffer which contains logic circuitry for routing a subset of the instruction bits from bit locations in the buffer to destination logic circuitry;

an instruction buffer interdependency checking logic block responsive to said routing of the instruction bits, further comprising,

program instructions provided in a pipeline architecture; and

an information key established as instruction security commands at a plurality of steps in said pipeline architecture, wherein an arithmetic logic unit (ALU) provides variability of logic circuitry for execution of encrypted instruction op codes or standard instruction op codes that provide standard instruction operation types.

11. The microprocessor of claim 10, further comprising:

the key stored in more than one memory cell type including a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (E²PROM), and a Random Access Memory (RAM);

the keys including bits expandable into a larger set of bits which control the instruction decoder, signal routing, and logic gate reconfiguration;

a serial number in ROM which participates in the allocation of logic gates and routing of signals, and communicated to the compiler to inform the compiler of custom allocation and routing; and

the key providing a capability of controlling signal routing, and logic gate reconfiguration whether the instructions are encrypted instructions or standard instructions.

12. The microprocessor of claim 11, further comprising an output register for data results able to contain both correct results and plausible wrong results which are in word locations in the output register coordinated by the key.

13. The microprocessor of claim 12, wherein:

a plurality of reconfigurable logic gates calculate results of execution of an instruction;

said plurality of the logic gates includes provisions for accepting correct data operands and plausible wrong data operands; and

said plurality of the logic gates includes provisions for outputting correct results along with plausible wrong results.

14. The microprocessor of claim 13, wherein the output register for data results contain both correct results and plausible wrong results which are in word locations in the output register, the locations of the results coordinated by the key.

15. The microprocessor of claim 14, further comprising:

a plurality of the memory locations dispersed within a layout;

a plurality of reconfigurable logic gates able to calculate results of execution of an instruction;

said plurality of the logic gates including provisions for accepting correct data operands and plausible wrong data operands; and

said plurality of the logic gates including provisions for outputting correct results along with plausible wrong results.

16. The microprocessor of claim 15, further comprising:

the key providing a capability of re-allocating memory resources and register resources;

a serial number in ROM which participates in the allocation of logic gates and routing of signals; and

the serial number used in combination with the key in providing said capability.

17. A particularly configurable microprocessor for processing computer programs which are selectively operable on said particularly configurable microprocessor, comprising:

a store for key shared with a compiler, the key used by the compiler to encrypt standard instructions into encrypted instructions;

an instruction buffer which contains logic circuitry for routing a subset of the instruction bits from bit locations in the buffer to destination logic circuitry;

an instruction buffer interdependency checking logic block responsive to said routing of the instruction bits, further comprising;

program instructions provided in a pipeline architecture; and

information keys established as instruction security commands at a plurality of steps in said pipeline architecture, wherein an arithmetic logic unit (ALU) provides variability of logic circuitry for execution of encrypted instruction op codes or standard instruction op codes that provide standard instruction operation types.

18. A particularly configurable microprocessor for processing computer programs which are selectively operable on said particularly configurable microprocessor, comprising:

a store for key shared with a compiler, the key used by the compiler to encrypt standard instructions into encrypted instructions;

an instruction buffer which contains logic circuitry for routing a subset of the instruction bits from bit locations in the buffer to destination logic circuitry

an instruction buffer interdependency checking logic block responsive to said routing of the instruction bits, wherein the logic circuitry includes reconfigurable logic gates, said reconfigurable logic gates making provisions for outputting correct results along with plausible wrong results.

19. A particularly configurable microprocessor for processing computer programs which are selectively operable on said particularly configurable microprocessor, comprising:

a store for key shared with a compiler, the key used by the compiler to encrypt standard instructions into encrypted instructions,

an instruction buffer which contains logic circuitry for routing a subset of the instruction bits from bit locations in the buffer to destination logic circuitry;

an instruction buffer interdependency checking logic block responsive to said routing of the instruction bits, further comprising;

an output register for data results capable of providing data containing both correct results and plausible wrong results; and

the correct results provided in word locations in the output register coordinated by the key.

20. A particularly configurable microprocessor for processing computer programs which are selectively operable on said particularly configurable microprocessor, comprising:

a store for key shared with a compiler, the key used by the compiler to encrypt standard instructions into encrypted instructions;

an instruction buffer which contains logic circuitry for routing a subset of the instruction bits from bit locations in the buffer to destination logic circuitry;

an instruction buffer interdependency checking logic block responsive to said routing of the instruction bits, wherein the instruction buffer interdependency checking logic includes any combination of the following,

multiplexers to select a subset of bits from each long instruction word in the instruction buffer to be logically combined to match a sequencer value;

a sequencer incremented at times determined by the key and which is reset upon the occurrence of the sequencer reset code in the instruction buffer;

distribution of bits for one encrypted instruction op code across several long instruction words in the instruction buffer;

distribution of several encrypted instruction op codes around the long instruction words in the instruction buffer;

a program counter which does not normally increment by one, but which increments by some other constant or variable amount determined by the serial number, the key, and the sequencer value so that encrypted instruction op codes which will be used sequentially in time do not occur sequentially in the instruction buffer, and for which, the time sequential chosen instruction op codes are selected by the multiplexer controlled by the key, the serial number, and the sequencer;

error correction circuits controlled by the key, sequencer, and supplementary error correcting codes received from the instruction buffer by means of the multiplexers; and

dependency validation codes received through the multiplexer of the instruction buffer checked by logic circuits that depend on the key, the serial number, instruction bits, and camouflage bits.

21. The microprocessor of claim 20, further comprising dependency validation codes received through the multiplexer of the instruction buffer checked by logic circuits that depend on the key, the serial number, instruction bits, and camouflage bits so that incorrect validation bits provide an alarm.

22. The microprocessor of claim 21, wherein upon receipt of said alarm, the interdependency checking logic writes an audit code and is capable of terminating program execution.

23. A particularly configurable microprocessor for processing computer programs which are selectively operable on said particularly configurable microprocessor, comprising:

a store for key shared with a compiler, the key used by the compiler to encrypt standard instructions into encrypted instructions;

an instruction buffer which contains logic circuitry for routing a subset of the instruction bits from bit locations in the buffer to destination logic circuitry

an instruction buffer interdependency checking logic block responsive to said routing of the instruction bits, further comprising,

a plurality of storage locations for keys, with the keys further determining storage locations of satellite keys and satellite access flags, said locations intentionally varied;

key-dependent storage of remote access approval flags, the remote access approval flags encoded so as to obscure the locations of said approval flags;

logic circuitry for using a null key for a default unencrypted instruction set with partitioning of memory resources between those used for with null key programs and those used for the keyed programs; and

logic circuitry for selecting from any of several stored keys so that several independent encrypted and unencrypted programs may be executed sequentially by installing each different key when needed, which also reallocates memory and register resources that are securely partitioned from each other.

24. The microprocessor of claim 23, further comprising logic for requiring network handshaking, the network handshaking further used to provide additional key information for continued operation.