Flash EEprom system

• US 6,757,842 B2
• Filed: 09/06/2002
• Issued: 06/29/2004
• Est. Priority Date: 04/13/1989
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Mehrotra, Sanjay, Norman, Robert D.
• Primary Examiner(s): HUA, LY
• Application Number:
  US10/237,456
• Publication Number:
  US 20030014689A1
• Time in Patent Office: 662 Days
• Field of Search: 714/8, 714/10, 714/11, 365/185.12, 365/189.07
• US Class Current: 714/6.32
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 : Hybrid storage device
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5621 : using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 : Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 : Erasing circuits
• CPC Class Codes: G11C 16/10 : Programming or data input circuits
• CPC Class Codes: G11C 16/16 : for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 : Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 : Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 : Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3454 : Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 : Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 : Multilevel programming verification
• CPC Class Codes: G11C 2211/5634 : Reference cells
• CPC Class Codes: G11C 2211/5643 : Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 2216/18 : Flash erasure of all the cells in an array, sector or block simultaneously
• CPC Class Codes: G11C 29/00 : Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/26 : Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 : Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 : in solid state disks
• CPC Class Codes: G11C 29/82 : for EEPROMs
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Claims

1. A method of operating a memory system with a host system, wherein the memory system includes an array of non-volatile memory cells on an integrated circuit memory chip that is partitioned into a plurality of blocks that individually include a distinct group of memory cells that are erasable together as a unit, comprising:

utilizing said memory chip and a memory controller within a card that is removably connectable to the host system, said controller being connectable to the host system for controlling operation of the memory system when the card is connected thereto,

operating individual blocks of memory cells with non-overlapping portions thereof storing at least user data and overhead information,

detecting a predefined condition when individual blocks become unusable and linking the addresses of such unusable blocks with addresses of other blocks that are useable,

causing the controller, in response to receipt from the host system of an address in a format designating at least one mass memory storage block, to generate an address of a non-volatile memory block that corresponds to said at least one mass memory storage block,

accessing a usable block of the memory system, if the block with the generated address is unusable, by referring to the linked address of another block that is usable and then accessing that other block,

either writing data to, or reading data from, the user data portion of the accessed usable block, and

either writing to, or reading from, said overhead portion of the accessed usable block, information related to either the accessed usable block or data stored in the user data portion of said accessed useful block.

2. The method according to claim 1, wherein the detecting of the predefined condition includes detecting when individual blocks become defective.

3. The method according to claim 2, wherein the detecting of when individual blocks become defective includes determining when a number of individual defective memory cells within a block exceed a given number.

4. The method according to claim 1, wherein the user data portion of the individual non-volatile memory blocks has a capacity of 512 bytes.

5. The method according to claim 1, wherein the information stored in the overhead portion of the individual blocks includes an address of the respective ones of the individual blocks.

6. The method according to claim 1, wherein the information stored in the overhead portion of the individual blocks includes an error correction code calculated from data stored in the user data portions of corresponding ones of the individual blocks.

7. The method according to claim 1 wherein linking the address of unusable blocks with blocks that are useable includes maintaining a list within the card that links such unusable blocks with addresses of corresponding ones of the other blocks that are useable, and wherein accessing a usable block includes referring to the list to translate the address of the unusable block into an address of a usable block.

8. The method according to claim 1 wherein linking the address of such unusable blocks includes storing within individual ones of the defective blocks addresses of corresponding useable blocks, and wherein accessing a usable block corresponding to an unusable block includes referring to the useable block address stored in the unusable block.

9. The method according to claim 1, wherein causing the controller to generate an address of a non-volatile memory block includes doing so for a non-volatile memory block that corresponds to only one mass memory storage block, wherein the user data portion of the individual non-volatile memory blocks has a capacity that is substantially the same as a user data portion of said one mass memory storage block.

10. A method of operating a memory system with a host system, wherein the memory system includes an array of non-volatile memory cells on an integrated circuit memory chip that is partitioned into a plurality of blocks that individually include a distinct group of memory cells that are erasable together as a unit, comprising:

utilizing said memory chip and a memory controller within a card that is removably connectable to the host system, said controller being connectable to the host system for controlling operation of the memory system when the card is connected thereto,

operating individual blocks of memory cells with non-overlapping portions thereof storing at least user data and overhead information,

causing the controller, in response to receipt from the host system of an address in a format designating at least one mass memory storage block, to designate an address of at least one non-volatile memory block that corresponds with said at least one mass memory storage block,

either writing user data to, or reading user data from, the user data portion of said at least one non-volatile memory block, and

either writing to, or reading from, said overhead portion of said at least one non-volatile memory block, overhead data related either to said at least one non-volatile memory block or to data stored in the user data portion of said at least one non-volatile memory block.

11. The method of claim 10, wherein the user data portion of the individual blocks has a capacity of 512 bytes.

12. The method of claim 10, wherein the overhead data stored in said overhead portion of the individual blocks includes addresses of the individual blocks.

13. The method of claim 10, wherein partitioning the memory cells includes partitioning said memory cells within the individual blocks to include an additional portion of spare memory cells.

14. The method of claim 13, wherein the overhead data stored in said overhead portion of the individual blocks includes an identification of any defective cells within the user data portion of corresponding ones of said blocks, said method additionally comprising causing the controller to read the identification of defective cells from the overhead portion of said addressed at least one non-volatile memory block and then to substitute therefore other cells within the spare cell portion of the addressed at least one non-volatile memory block.

15. The method of claim 10, additionally comprising causing the controller to identify and store addresses of any defective non-volatile memory blocks within the array, and, wherein designating an address of a block includes, in response to designating an address of a defective block, substituting an address of another block instead.

16. The method of claim 10, wherein the individual blocks include only one user data portion and only one overhead data portion.

17. The method of claim 10, wherein writing to the accessed usable block includes programming the individual memory cells thereof into one of exactly two programmable states in order to store exactly one bit of data or information per cell.

18. The method of claim 10, wherein writing to the accessed usable block includes programming the individual memory cells thereof into one of more than two programmable states in order to store more than one bit of data or information per cell.

19. The method of claim 10, wherein the address of said at least one mass memory storage block is an address of at least one magnetic disk block.

20. The method of claim 10, wherein communication of mass memory storage block addresses and user data with the controller is in parallel over a bus.

21. A method of operating, with a host system, a non-volatile memory system that includes an array of non-volatile memory cells on an integrated circuit chip that is partitioned into blocks of memory cells that are erasable together as a unit, comprising:

providing said memory array and a memory controller within a card that is removably connectable to the host system, the controller being connectable to said host system for controlling operation of the memory array when the card is connected to the host system, and storage elements of the memory cells within said memory array being individually programmable into one of more than two distinct threshold level ranges corresponding to more than one bit of data per storage element,

causing the controller, in response to receipt from the host system of an address in a format designating at least one mass memory storage block, to designate an address of at least one non-volatile memory block that corresponds with said at least one mass memory storage block,

either writing user data to, or reading user data from, said at least one non-volatile memory block,

either writing to, or reading from, said at least one non-volatile memory block, overhead data related either to said at least one non-volatile memory block or to user data stored in said at least one non-volatile memory block, and

wherein the writing of user and overhead data includes programming the storage elements of the individual memory cells of the array into said one of more than two distinct threshold level ranges.

22. The method of claim 21, wherein the overhead data written into said at least one non-volatile memory block includes overhead data generated within the memory controller.

23. The method of claim 21, wherein the user data written into the individual blocks is substantially 512 bytes.

24. The method of claim 21, wherein the overhead data stored in said overhead portion of the individual blocks includes addresses of the individual blocks.

25. The method of claim 24, wherein the overhead data stored in said overhead portion of the individual blocks additionally includes, in those block that are defective, addresses of blocks being substituted therefor.

26. The method of claim 21, additionally comprising causing the controller to identify and store addresses of any defective non-volatile memory blocks within the array, and, wherein designating an address of said at least one memory block includes, in response to designating an address of a defective block, substituting an address of another block instead.

27. The method of claim 21, wherein the address of said at least one mass memory storage block includes an address of at least one magnetic disk block.

28. The method of claim 21, further comprising erasing data from a selected at least one of the individual blocks of memory cells by simultaneously applying an erase voltage to all of the memory cells within said selected at least one block, thereby to simultaneously erase any user data and associated overhead data contained in said at least one block.

29. The method of claim 28, wherein the memory array cells individually include erase gates, and the erase voltage is simultaneously applied to the erase gates of said selected at least one block of memory cells.

30. The method of claim 21, wherein the memory cell storage elements are conductive floating gates.

31. A method of operating a computer system including a processor and a memory system, wherein the memory system includes an array of non-volatile floating gate memory cells on an integrated circuit memory chip that is partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, comprising:

providing said memory chip and a memory controller within a card that is removably connectable to the computer system, said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system,

partitioning memory cells within individual sectors into at least a user data portion and an overhead portion,

detecting a predefined condition when individual sectors become unusable and linking the addresses of such unusable sectors with addresses of other sectors that are useable,

causing the controller, in response to receipt from the processor of an address in a format designating at least one magnetic disk sector, to generate an address of a non-volatile memory sector that corresponds to said at least one magnetic disk sector,

accessing a usable sector of the memory system, if the sector with the generated address is unusable, by referring to the linked address of another sector that is usable and then accessing that other sector,

either writing data to, or reading data from, the user data portion of the accessed usable sector, and

either writing to, or reading from, said overhead portion of the accessed usable sector, information related to either the accessed usable sector or data stored in the user data portion of said accessed useful sector.

32. The method according to claim 31, wherein the detecting of the predefined condition includes detecting when individual sectors become defective.

33. The method according to claim 32, wherein the detecting of when individual sectors become defective includes determining when a number of individual defective memory cells within a sector exceed a given number.

34. The method according to claim 31, wherein the user data portion of the individual non-volatile memory sectors has a capacity of substantially 512 bytes.

35. The method according to claim 31, wherein the information stored in the overhead portion of the individual sectors includes an address of the respective ones of the individual sectors.

36. The method according to claim 31, wherein the information stored in the overhead portion of the individual sectors includes an error correction code calculated from data stored in the user data portions of corresponding ones of the individual sectors.

37. The method according to claim 31, wherein linking the address of unusable sectors with sectors that are useable includes maintaining a list within the card that links such unusable sectors with addresses of corresponding ones of the other sectors that are useable, and wherein accessing a usable sector includes referring to the list to translate the address of the unusable sector into an address of a usable sector.

38. The method according to claim 31, wherein linking the address of such unusable sectors includes storing within individual ones of the defective sectors addresses of corresponding useable sectors, and wherein accessing a usable sector corresponding to an unusable sector includes referring to the useable sector address stored in the unusable sector.

39. The method according to claim 31, wherein causing the controller to generate an address of a non-volatile memory sector includes doing so for a non-volatile memory sector that corresponds to only one magnetic disk sector, wherein the user data portion of the individual non-volatile memory sectors has a capacity that is substantially the same as a user data portion of said one magnetic disk sector.

40. A method of operating a computer system including a processor and a memory system, wherein the memory system includes an array of non-volatile floating gate memory cells on an integrated circuit chip that is partitioned into a plurality of sectors that individually include a distinct group of said array of memory cells that are erasable together as a unit, comprising:

providing said memory chip and a memory controller within a card that is removably connectable to the computer system, said controller being connectable to said processor for controlling operation of the array when the card is connected to the computer system,

partitioning memory cells within individual sectors into at least a user data portion and an overhead portion,

causing the controller, in response to receipt from the processor of an address in a format designating at least one magnetic disk sector, to designate an address of at least one non-volatile memory sector that corresponds with said at least one magnetic disk sector,

either writing user data to, or reading user data from, the user data portion of said at least one non-volatile memory sector, and

either writing to, or reading from, said overhead portion of said at least one non-volatile memory sector, overhead data related either to said at least one non-volatile memory sector or to data stored in the user data portion of said at least one non-volatile memory sector.

41. The method of claim 40, wherein the user data portion of the individual sectors has a capacity of substantially 512 bytes.

42. The method of claim 40, wherein the overhead data stored in said overhead portion of the individual sectors includes addresses of the individual sectors.

43. The method of claim 40, wherein partitioning the memory cells includes partitioning said memory cells within the individual sectors to include an additional portion of spare memory cells.

44. The method of claim 43, wherein the overhead data stored in said overhead portion of the individual sectors includes an identification of any defective cells within the user data portion of corresponding ones of said sectors, said method additionally comprising causing the controller to read the identification of defective cells from the overhead portion of said addressed at least one non-volatile memory sector and then to substitute therefore other cells within the spare cell portion of the addressed at least one non-volatile memory sector.

45. The method of claim 40, additionally comprising causing the controller to identify and store addresses of any defective non-volatile memory sectors within the array, and, wherein designating an address of a sector includes, in response to designating an address of a defective sector, substituting an address of another sector instead.

46. The method of claim 40, wherein the individual sectors include only one user data portion and only one overhead data portion.

47. A method of operating a memory system with a host system that includes a processor, wherein the memory system includes one or more integrated circuit chips individually including an array of non-volatile memory cells partitioned into a plurality of sectors that individually include a distinct group of memory cells that are erasable together as a unit, comprising:

providing said one or more chips and a memory controller within a card that is removably connectable to the host system, said controller being connectable to said processor for controlling operation of the memory system when the card is connected to the host system,

operating memory cells within individual sectors with at least a user data portion and an overhead portion,

detecting a predefined condition when individual sectors become unusable and linking the addresses of such unusable sectors with addresses of other sectors that are useable,

causing the controller, in response to receipt from the processor of an address in a format designating at least one mass memory storage block, to generate an address of a non-volatile memory sector that corresponds to said at least one mass memory storage block,

accessing a usable sector of the memory system, if the sector with the generated address is unusable, by referring to the linked address of another sector that is usable and then accessing that other sector,

either writing data to, or reading data from, the user data portion of the accessed usable sector, and

either writing to, or reading from, said overhead portion of the accessed usable sector, information related to either the accessed usable sector or data stored in the user data portion of said accessed useful sector.

48. The method according to claim 47, wherein the detecting of the predefined condition includes detecting when individual sectors become defective.

49. The method according to claim 48, wherein the detecting of when individual sectors become defective includes determining when a number of individual defective memory cells within a sector exceed a given number.

50. The method according to claim 47, wherein the user data portion of the individual non-volatile memory sectors has a capacity of substantially 512 bytes.

51. The method according to claim 47, wherein the information stored in the overhead portion of the individual sectors includes an address of the respective ones of the individual sectors.

52. The method according to claim 47, wherein the information stored in the overhead portion of the individual sectors includes an error correction code calculated from data stored in the user data portions of corresponding ones of the individual sectors.

53. The method according to claim 47, wherein linking the address of unusable sectors with sectors that are useable includes maintaining a list within the card that links such unusable sectors with addresses of corresponding ones of the other sectors that are useable, and wherein accessing a usable sector includes referring to the list to translate the address of the unusable sector into an address of a usable sector.

54. The method according to claim 47, wherein linking the address of such unusable sectors includes storing within individual ones of the defective sectors addresses of corresponding useable sectors, and wherein accessing a usable sector corresponding to an unusable sector includes referring to the useable sector address stored in the unusable sector.

55. The method according to claim 47, wherein causing the controller to generate an address of a non-volatile memory sector includes doing so for a non-volatile memory sector that corresponds to only one mass memory storage block, wherein the user data portion of the individual non-volatile memory sectors has a capacity that is substantially the same as a user data portion of said one mass memory storage block.

56. The method of any of claims 47-55, wherein writing to the accessed usable sector includes programming the individual memory cells thereof into exactly two programmable states in order to store exactly one bit of data or information per cell.

57. The method of claim 56, wherein the address of said at least one mass memory storage block is an address of at least one magnetic disk sector.

58. The memory of any one of claims 47-55, wherein writing to the accessed usable sector includes programming the individual memory cells thereof into one of more than two programmable states in order to store more than one bit of data information per cell.

59. The method of claim 58, wherein the address of said at least one mass memory storage block is an address of at least one magnetic disk sector.

60. The method any one of claims 47-55, wherein communication of mass memory storage block addresses and user data with the controller is in parallel over a bus.

61. A method of operating a memory system with a host system that includes a processor, wherein the memory system includes one or more integrated circuit chips individually including an array of non-volatile floating gate memory cells partitioned into a plurality of sectors that individually include a distinct group of memory cells that are erasable together as a unit, comprising:

providing said one or more of the memory integrated circuit chips and a memory controller within a card that is removably connectable to the host system, said controller being connectable to said processor for controlling operation of the memory system when the card is connected to the host system,

operating memory cells within individual sectors with at least a user data portion and an overhead portion,

causing the controller, in response to receipt from the processor of an address in a format designating at least one mass memory storage block, to designate an address of at least one non-volatile memory sector that corresponds with said at least one mass memory storage block,

either writing user data to, or reading from, the user data portion of said at least one non-volatile memory sector, and

either writing to, or reading from, said overhead portion of said at least one non-volatile memory sector, overhead data related either to said at least one non-volatile memory sector or to data stored in the user data portion of said at least one non-volatile memory sector.

62. The method of claim 61, wherein the user data portion of the individual sectors has a capacity of substantially 512 bytes.

63. The method of claim 61, wherein the overhead data stored in said overhead portion of the individual sectors includes addresses of the individual sectors.

64. The method of claim 61, wherein partitioning the memory cells includes partitioning said memory cells within the individual sectors to include an additional portion spare memory cells.

65. The method of claim 64, wherein the overhead data stored in said overhead portion of the individual sectors includes an identification of any defective cells within the user data portion of corresponding ones of said sectors, said method additionally comprising causing the controller to read the identification of defective cells from the overhead portion of said addressed at least one non-volatile memory sector and then to substitute therefore other cells within the spare cell portion of the addressed at least one non-volatile memory sector.

66. The method of claim 61, additionally comprising causing the controller to identify and store addresses of any defective non-volatile memory sectors within the array, and, wherein designating an address of a sector includes, in response to designating an address of a defective sector, substituting an address of another sector instead.

67. The method of claim 61, wherein the individual sectors include only one user data portion and only one overhead data portion.

68. The method of any one of claims 61-67, wherein writing to said at least one non-volatile memory sector includes programming the individual memory cells thereof into one of exactly two programmable states in order to store exactly one bit of data per cell.

69. The method of claim 68, wherein the address of said at least one mass memory storage block is an address of at least one magnetic disk sector.

70. The method of any one of claims 61-67, wherein writing to said at least one non-volatile memory sector includes programming the individual memory cells thereof into one of more than two programmable states in order to store more than one bit of data per cell.

71. The method of claim 70, wherein the address of said at least one mass memory storage block is an address of at least one magnetic disk sector.

72. The method any one of claims 61-67, wherein communication of mass memory storage block addresses and user data with the controller is in parallel over a bus.