System and method for identifying and eliminating bottlenecks in integrated circuit designs

• US 6,757,877 B2
• Filed: 02/27/2002
• Issued: 06/29/2004
• Est. Priority Date: 02/27/2002
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Pavisic, Ivan, Stenberg, Robert
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US10/083,411
• Publication Number:
  US 20030163797A1
• Time in Patent Office: 853 Days
• Field of Search: 716/2, 716/6, 716/9, 716/10, 716/13, 716/5, 716/16, 714/733, 363/20
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method of integrated circuit design and a circuit design tool. Critical paths are identified in an integrated circuit design. Identified edges are weighted. Edges are assigned a higher weight responsive to the number of critical paths in which they are included. A net criticality is assigned to each weighted edge based upon the edge'"'"'s weight. Cells are re-placed and wired according to net criticality.

Claims

1. A method of integrated circuit design comprising steps of:

(a) placing and wiring an integrated circuit design;

(b) generating a slack graph of critical paths in the integrated circuit design;

(c) identifying bottlenecks in the critical paths wherein identifying bottlenecks comprises determining which nets in the slack graph include more critical paths when compared to other nets in the slack graph; and

(d) assigning a higher priority to reducing path edge delays at the bottlenecks than to other path edge delays.

2. A method of integrated circuit design comprising steps of:

(a) placing and wiring an integrated circuit design;

(b) generating a slack graph of critical paths in the integrated circuit design;

(c) identifying bottlenecks in the critical paths wherein identifying bottlenecks comprises determining which nets in the slack graph include more critical paths when compared to other nets in the slack graph identifying bottlenecks comprises calculating a forward node weight for each corresponding node wherein the forward node weight is equal to a minimum forward edge weight of all incoming edges to the corresponding node.

3. The method of claim 2 wherein step (c) comprises calculating a forward edge weight for each outgoing edge wherein the forward edge weight is equal to the forward node weight of the corresponding node plus a number of outgoing edges from the corresponding node minus one.

4. The method of claim 3 herein step (c) comprises calculating a reverse node weight for each corresponding node wherein the reverse node weight is equal to a minimum reverse edge weight of all outgoing edges from the corresponding node.

5. The method of claim 4 wherein step (c) comprises calculating a reverse edge weight for each incoming edge wherein the reverse edge weight is equal to the reverse node weight of the corresponding node plus a number of incoming edges to the corresponding node minus one.

6. The method of claim 5 wherein step (c) comprises summing the forward edge weight and the reverse edge weight for each edge in the slack graph.

7. The method of claim 6 wherein step (c) comprises setting a net weight value of a corresponding net equal to a minimum value of the sum of the forward edge weight and the reverse edge weight associated with each edge so that a relatively low net weight value indicates that the corresponding net belongs to a bottleneck.

8. A computer-readable medium having stored thereon a plurality of instructions, the plurality of instructions including instructions which, when executed by a processor, cause the processor to:

(a) place and wire an integrated circuit design;

(b) generate a slack graph of critical paths in the integrated circuit design;

(c) identify bottlenecks in the critical paths; and

(d) assigning a higher priority to reducing path edge delay, at the bottlenecks than to other path edge delays.

9. A computer-readable medium having stored thereon a plurality of instructions the plurality of instructions including instructions which, when executed by a processor, cause the processor to:

(a) place and wire an integrated circuit design;

(b) generate a slack graph of critical paths in the integrated circuit design; and

(c) identify bottlenecks in the critical paths wherein identifying bottlenecks comprises calculating a forward node weight for each corresponding node wherein the forward node weight is equal to a minimum forward edge weight of all incoming edges to the corresponding node.

10. The computer-readable medium of claim 9 wherein step (c) comprises calculating a forward edge weight for each outgoing edge wherein the forward edge weight is equal to the forward node weight of the corresponding node plus a number of outgoing edges from the corresponding node minus one.

11. The computer-readable medium of claim 10 wherein step (c) comprises calculating a reverse node weight for each corresponding node wherein the reverse node weight is equal to a minimum reverse edge weight of all outgoing edges from the corresponding node.

12. The computer-readable medium of claim 11 wherein step (c) comprises calculating a reverse edge weight for each incoming edge wherein the reverse edge weight is equal to the reverse node weight of the corresponding node plus a number of incoming edges to the corresponding node minus one.

13. The computer-readable medium of claim 12 wherein step (c) comprises the forward edge weight and the reverse edge weight for each edge in the slack graph.

14. The computer-readable medium of claim 13 wherein step (c) comprises a net weight value of a corresponding net equal to a minimum value of the mum of the forward edge weight and the reverse edge weight associated with each edge so that a relatively low net weight value indicates that the corresponding net belongs to a bottleneck.