Self-describing IP package for enhanced platform based SOC design

• US 6,757,882 B2
• Filed: 04/24/2002
• Issued: 06/29/2004
• Est. Priority Date: 06/16/2001
• Status: Expired due to Term

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Wilson, John, Brouhard, Michael C., Chen, Michael Y.
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Dimyan, Magid Y
• Application Number:
  US10/132,587
• Publication Number:
  US 20030009658A1
• Time in Patent Office: 797 Days
• Field of Search: 716/12, 716/1-7, 716/17-18, 716/14, 703/14
• US Class Current: 716/102
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation

Abstract

An IP package is formed with at least one of one or more components of an IP block and one or more pointers to locations where the components can be retrieved, and machine readable connectivity descriptions describing how the IP block is to be connected to include the IP block in an integrated circuit. In one embodiment, the connectivity descriptions include physical pin, implemented bus signals, handling of unimplemented bus signals, and mapping descriptions. In various embodiments, the IP package may further include one or more selected ones of customizable attribute, UI choice elements, embedded and/or diagnostic software, test vectors, supplemental generators and verification environment configuration requirement descriptions. The self-describing packaging advantageously enables an EDA tool suite to offer and facilitate selection of the IP block for a SOC design.

Claims

1. An IP package comprising:

a selected one of one or more machine readable components of an IP block and one or more machine readable pointers pointing to one or more locations from which the one or more components of the IP block can be retrieved;

machine readable descriptions describing customizable attributes of said one or more components; and

machine readable connectivity descriptions describing how the IP block is to be connected to include the IP block as part of an integrated circuit (IC).

2. The IP package of claim 1, wherein said IP block comprises a plurality of pins, and said machine readable connectivity descriptions comprise machine readable descriptions of said pins.

3. The IP package of claim 1, wherein said machine readable connectivity descriptions comprise machine readable descriptions of implemented bus signals of a known bus.

4. The IP package of claim 1, wherein said IP block comprises a plurality of pins, and said machine readable connectivity descriptions comprise machine readable descriptions of said pins, implemented bus signals of a known bus, and mapping of said pins to said implemented bus signals of the known bus.

5. The IP package of claim 4, wherein said machine readable connectivity descriptions further comprise machine readable handling descriptions of unimplemented bus signals of a known bus, and said machine readable handling descriptions of unimplemented bus signals of a known bus comprise a reference to a bus decoding template comprising default handling of unimplemented bus signals of said known bus.

6. The IP package of claim 5, wherein said IP package further comprises machine readable descriptions describing customizable attributes of said components of said IP block, and said machine readable descriptions describing customizable attributes of said components of said IP block comprise descriptions of methods of resolution for said customizable attributes described.

7. The IP package of claim 6, wherein said IP package further comprises machine readable descriptions describing one or more supplemental generators associated with said IP block, to be executed at designated phases of a design/verification process, to transform design information of said IC, from a first state to a second state;

and machine readable descriptions describing one or more verification environment configuration requirements of said IP block for one or more verification environments.

8. The IP package of claim 1, wherein said machine readable descriptions describing customizable attributes includes a plurality of predefined choices for designer customization of said component, wherein said predefined choices are presented to said designer when the designer selects said component.

9. The IP package of claim 8, wherein said machine readable descriptions describing customizable attributes of said components of said IP block comprise descriptions of methods of resolution for said customizable attributes described.

10. The IP package of claim 9, wherein said descriptions of methods of resolution for said customizable attributes described comprise at least one of a first description of a first method of resolution through user input, and a second description of a second method of resolution through dependency on one or more other customizable attributes.

11. The IP package of claim 1, wherein said IP package further comprises machine readable descriptions describing user interface elements for use to prompt a designer in specifying customizable attributes of said IP block.

12. The IP package of claim 1, wherein said IP package further comprises machine readable descriptions describing at least a selected one of one or more embedded software and one or more diagnostic software of said IP block.

13. The IP package of claim 1, wherein said IP package further comprises machine readable descriptions describing one or more supplemental generators associated with said IP block, to be executed at designated phases of a design/verification process, to transform design information of said IC, from a first state to a second state.

14. The IP package of claim 1, wherein said IP package further comprises machine readable descriptions describing one or more verification environment configuration requirements of said IP block for one or more verification environments.

15. An IP package comprising:

a selected one of one or more machine readable components of an IP block and one or more machine readable pointers pointing to one or more locations from which the one or more components of the IP block can be retrieved; and

machine readable connectivity descriptions describing how the IP block is to be connected to include the IP block as part of an integrated circuit (IC),

wherein said machine readable connectivity descriptions comprise machine readable handling descriptions of unimplemented bus signals of a known bus.

16. The IP package of claim 15, wherein said machine readable handling descriptions of unimplemented bus signals of a known bus comprise a reference to a bus decoding template comprising default handling of unimplemented bus signals of said known bus.

17. An IP package comprising:

a selected one of one or more machine readable components of an IP block and one or more machine readable pointers pointing to one or more locations from which the one or more components of the IP block can be electronically retrieved; and

machine readable connectivity descriptions describing customizable attributes of said components of said IP, including user interface elements for use to prompt a designer in specifying said customizable attributes when including said IP block in an integrated circuit (IC).

18. The IP package of claim 17, wherein said machine readable descriptions describing customizable attributes of components of said IP block comprise descriptions of methods of resolution for said customizable attributes described.

19. The IP package of claim 18, wherein said descriptions of method of resolution for said customizable attributes described comprise at least one of a first description of a first method of resolution through user input, and a second description of a second method of resolution through dependency on one or more other customizable attributes.

20. The IP package of claim 17, wherein said IP package further comprises machine readable descriptions describing one or more supplemental generators of said IP block to be executed at designated design/verification phases of a design process, to transform design information of said IC, from a first state to a second state.

21. The IP package of claim 17, wherein said IP package further comprises machine readable descriptions describing one or more verification environment configuration requirements of said IP block for one or more verification environments.

22. An IP package comprising:

a selected one of one or more machine readable components of an IP block and one or more machine readable pointers pointing to one or more locations from which the one or more components of the IP block can be electronically retrieved; and

machine readable descriptions describing one or more supplemental design/verification generators associated with said IP block to be executed at designated design/verification phases of a design process, to transform design information of an integrated circuit (IC) including said IP block, from a first state to a second state.

23. The IP package of claim 22, wherein said IP package further comprises machine readable descriptions describing one or more verification environment configuration requirements of said IP block for one or more verification environments.

24. A machine implemented method comprising:

creating a selected one of one or more machine readable components of an IP block and one or more machine readable pointers pointing to one or more locations from which the one or more components of the IP block can be retrieved;

using a compatibility analyzer to present a user with a limited list of components that are compatible with components that said user has previously added to said IP block;

receiving a user selection of one of said listed components for addition to said IP block;

creating machine readable connectivity descriptions describing how the IP block is to be connected to include the IP block as part of an integrated circuit (IC); and

forming an IP package with at least said created components/pointers to locations of the components, and said connectivity description of said IP block.

25. The method of claim 24, wherein said IP block comprises a plurality of pins, and said creating of machine readable connectivity descriptions comprises creating machine readable descriptions of said pins.

26. The method of claim 24, wherein said creating of machine readable connectivity descriptions comprises creating machine readable descriptions of implemented bus signals of a known bus.

27. The method of claim 24, wherein said creating of machine readable connectivity descriptions comprises creating machine readable handling descriptions of unimplemented bus signals of a known bus.

28. The method of claim 27, wherein said creating of machine readable handling descriptions of unimplemented bus signals of a known bus comprises creating a reference to a bus decoding template comprising default handling of unimplemented bus signals of said known bus.

29. The method of claim 24, wherein said IP block comprises a plurality of pins, and said creating of machine readable connectivity descriptions comprises creating machine readable descriptions of said pins, implemented bus signals of a known bus, and mapping of said pins to said implemented bus signals of the known bus.

30. The method of claim 29, wherein said creating of machine readable connectivity descriptions further comprises creating machine readable handling descriptions of unimplemented bus signals of a known bus, and said creating of machine readable handling descriptions of unimplemented bus signals of a known bus comprises creating a reference to a bus decoding template comprising default handling of unimplemented bus signals of said known bus.

31. The method of claim 30, wherein

said method further comprises creating machine readable descriptions describing customizable attributes of said components of said IP block, and said creating of machine readable descriptions describing customizable attributes of said components of said IP block comprises creating descriptions of methods of resolution for said customizable attributes described; and

said forming of an IP package further includes said machine readable descriptions describing customizable attributes of said IP block.

32. The method of claim 31, wherein said method further comprises

creating machine readable descriptions describing one or more supplemental generators associated with said IP block, to be executed at designated phases of a design/verification process, to transform design information of said IC, from a first state to a second state, and

creating machine readable descriptions describing one or more verification environment configuration requirements of said IP block for one or more verification environments;

and said forming of an IP package further includes said machine readable descriptions describing said one or more supplemental generators of said IP block, and said machine readable descriptions describing said one or more verification environment configuration requirements of said IP block.

33. The method of claim 24 wherein said method further comprises creating machine readable descriptions describing customizable attributes of said components of said IP block, and said forming of an IP package further includes said machine readable descriptions describing said customizable attributes of said components of said IP block.

34. The method of claim 33, wherein said creating of machine readable descriptions describing customizable attributes of said components of said IP block comprises creating descriptions of methods of resolution for said customizable attributes described.

35. The method of claim 34, wherein said creating of descriptions of methods of resolution for said customizable attributes described comprises creating at least one of a first description of a first method of resolution through user input, and a second description of a second method of resolution through dependency on one or more other customizable attributes.

36. The method of claim 24, wherein said method further comprises creating machine readable descriptions describing user interface elements for use to prompt a designer in specifying customizable attributes of said IP block, and said forming of an IP package further includes said machine readable descriptions describing said user interface elements.

37. The IP package of claim 24, wherein said method further comprises machine readable descriptions describing at least a selected one of one or more embedded software and one or more diagnostic software of said IP block, and said forming of an IP package further includes said machine readable descriptions describing said one or more embedded/diagnostic software of said IP block.

38. The method of claim 24, wherein said method further comprises machine readable descriptions describing one or more supplemental generators associated with said IP block, to be executed at designated phases of a design/verification process, to transform design information of said IC, from a first state to a second state, and said forming of an IP package further includes said machine readable descriptions describing said supplemental generators associated with said IP block.

39. The method of claim 24, wherein said method further comprises creating machine readable descriptions describing one or more verification environment configuration requirements of said IP block for one or more verification environments, and said forming of an IP package further includes said machine readable descriptions describing said one or more verification environment configuration requirements of said IP block.

40. A machine implemented method comprising:

creating a selected one of one or more machine readable components of an IP block and one or more machine readable pointers pointing to one or more locations from which the one or more components of the IP block can be electronically retrieved;

creating machine readable descriptions describing customizable attributes of said components of said IP, including user interface elements for use to prompt a designer in specifying said customizable attributes when including said IP block in an integrated circuit (IC); and

forming an IP package with said one or more components/pointers to locations of said components of said IP block, and said machine readable descriptions describing customizable attributes of said components of said IP block.

41. The method of claim 40, wherein said creating of machine readable descriptions describing customizable attributes of components of said IP block comprises creating descriptions of methods of resolution for said customizable attributes described.

42. The method of claim 41, wherein said creating of descriptions of method of resolution for said customizable attributes described comprises creating at least one of a first description of a first method of resolution through user input, and a second description of a second method of resolution through dependency on one or more other customizable attributes.

43. The method of claim 41, wherein said method further comprises creating machine readable descriptions describing one or more supplemental generators of said IP block to be executed at designated design/verification phases of a design process, to transform design information of said IC, from a first state to a second state, and said forming of an IP package further includes said machine readable descriptions describing said supplemental generators.

44. The method of claim 41, wherein said method further comprises creating machine readable descriptions describing one or more verification environment configuration requirements of said IP block for one or more verification environments, and said forming of an IP package further includes said machine readable descriptions describing said one or more verification environment configuration requirements.

45. A machine implemented method comprising:

creating a selected one of one or more machine readable components of an IP block and one or more machine readable pointers pointing to one or more locations from which the one or more components of the IP block can be electronically retrieved;

creating machine readable descriptions describing one or more supplemental generators associated with said IP block to be executed at designated design/verification phases of a design process, to transform design information of an integrated circuit (IC) including said IP block, from a first state to a second state; and

forming an IP package with said one or more components/pointers to locations of said components of said IP block, and said supplemental generators associated with said IP block.

46. The method of claim 45, wherein said method further comprises creating machine readable descriptions describing one or more verification environment configuration requirements of said IP block for one or more verification environments, and said forming of an IP package further includes said machine readable descriptions describing said verification environment configuration requirements of said IP block.