Method and structure for buried circuits and devices

• US 6,759,282 B2
• Filed: 06/12/2001
• Issued: 07/06/2004
• Est. Priority Date: 06/12/2001
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Campbell, John E., Srikrishnan, Kris V., Devine, William T.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US09/879,530
• Publication Number:
  US 20020185684A1
• Time in Patent Office: 1,120 Days
• Field of Search: 438/149, 438/154, 438/164, 438/295, 438/300, 438/404, 438/412, 438/425, 438/618, 438/161, 438/622, 438/151, 438/270, 438/282, 438/589, 438/455, 438/405, 438/530, 438/155, 438/197, 438/243, 438/459, 438/30, 257/306, 257/347-352
• US Class Current: 438/149
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor

Abstract

A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Claims

1. A method of fabricating an electronic device using an SOI technique, said SOI technique resulting in formation of a buried oxide layer, said method comprising:

fabricating at least one first component of said electronic device in a first single crystal semiconductor layer; and

depositing a conductive material to fabricate at least one second component of said electronic device in a second single crystal semiconductor layer below and separated from said first single crystal semiconductor layer by said buried oxide layer, wherein one of said second components comprises a component embedded in a substrate beneath said buried oxide layer and said buried oxide layer is thinned locally to perform a function integral to said electronic device;

said fabricating further comprising;

forming a trench in said substrate;

forming an insulator on at least one of a sidewall surface and a bottom surface; and

depositing said conductive material within said trench such that said deposited conductive material and a top surface of said substrate are essentially planar.

2. The method of claim 1, wherein one of said second components comprises a buried gate and said buried oxide layer is made thinner locally over said buried gate to provide a gate oxide for said buried gate.

3. The method of claim 1, wherein one of said second components is a body contact for an overlying gate and said buried oxide layer is not formed over said component.

4. The method according to claim 1, wherein said at least one first component is initially fabricated on a first wafer and said at least one second component is initially fabricated on a second wafer, and said SOI fabrication comprises bonding said first wafer and said second wafer to form said buried oxide layer.

5. The method according to claim 1, wherein said buried oxide layer is formed by implanting oxygen.

6. A device fabricated according to claim 1.

7. A method of fabricating an electronic circuit according to claim 1 having a plurality of electronic devices further comprising:

forming interconnector of conductive material to interconnect at least two of said plurality of electronic devices, said interconnector at least partially enclosed by said buried oxide.

8. An electronic chip fabricated using the method of claim 7.

9. The method of claim 1 wherein said conductive material is deposited within a trench etched through said buried oxide layer into said second single crystal semiconductor layer.

10. A method of fabricating a DRAM cell using an SOI technique on a substrate, said SOI technique resulting in formation of at least one buried oxide layer, said method comprising:

forming a buried capacitor beneath said buried oxide layer;

forming a gate beneath said buried oxide layer;

subsequently, forming an FET source region and drain region on top of said buried oxide layer, said gate being adapted to operate a FET channel between said source region and said drain region; and

interconnecting said capacitor to one of said source region or drain region with a via penetrating said buried oxide layer, said via comprised of a conductive material.

11. A method of fabricating a DRAM cell array according to claim 10, further comprising:

fabricating an array of DRAM cells according to the method of claim 10

wherein said gate is formed beneath said buried oxide layer for a first set of DRAM cells in said array and said gate is formed on top of said buried oxide layer for a second set of DRAM cells.

12. The method of claim 10, wherein said buried capacitor comprises a buried conductive material encased by an insulation layer separating said conductive material from said substrate, said method further comprises:

forming an insulation layer in a trench in said substrate to be beneath said buried oxide layer; and

filling a region formed by said insulation layer with a conductive material.

13. A DRAM cell having a structure in accordance with claim 10.

14. A method of fabricating a DRAM cell using an SOI technique, said SOI technique resulting in formation of at least one buried oxide (BOX) layer, whereby a capacitor for said DRAM cell is formed by a process comprising:

forming a buried electrode in a substrate, wherein said buried electrode serves as a lower capacitor charge plate; and

forming a diffusion link between the diffusion region of a transistor located on a upper side of said BOX and a region to comprise an upper charge plate of said capacitor, whereby said upper charged plate of said capacitor is formed on an upper side of said BOX when impressing a bias voltage on said buried electrode.

15. The method of claim 14, wherein said capacitor insulator comprises at least a portion of said buried oxide layer.

16. The method of claim 14, wherein said capacitor insulator comprises an insulation material different from said buried oxide layer.

17. The method of claim 14, further comprising:

forming an area of insulator material and a capacitor electrode above a device layer, overlying the BOX layer, part of said area located above said buried capacitor, and a conducting link in the device layer electrically connecting the respective charge plate regions of the buried and overlying capacitors, thereby increasing the value of capacitor in said DRAM cell.

18. A DRAM cell having a structure in accordance with claim 14.

19. A method of fabricating a dynamic two-phase shift register, said method comprising:

forming a buried oxide layer using an SOI technique;

forming a plurality of FET transistors to be in a device layer above said buried oxide layer;

forming a first clock signal conductor on top of said device layer; and

forming a second clock signal conductor below said device layer, said second clock signal conductor at least partially enclosed by said buried oxide layer.

20. An electronic chip containing a dynamic two-phase shift register fabricated according to the method of claim 19.