Double LDD devices for improved DRAM refresh
First Claim
1. A method of forming a semiconductor device, comprising:
- forming a single lightly doped region in a substrate adjacent a channel region, said channel region residing below a gate structure formed on said substrate;
forming a dielectric spacer on at least one side of said gate structure;
forming a heavily doped region in a portion of said substrate not covered by said dielectric spacer and adjacent said single lightly doped region;
narrowing said dielectric spacer on said at least one side of said gate structure; and
forming a double lightly doped region in said substrate between said heavily doped region and said single lightly doped region.
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Abstract
An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.
28 Citations
36 Claims
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1. A method of forming a semiconductor device, comprising:
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forming a single lightly doped region in a substrate adjacent a channel region, said channel region residing below a gate structure formed on said substrate;
forming a dielectric spacer on at least one side of said gate structure;
forming a heavily doped region in a portion of said substrate not covered by said dielectric spacer and adjacent said single lightly doped region;
narrowing said dielectric spacer on said at least one side of said gate structure; and
forming a double lightly doped region in said substrate between said heavily doped region and said single lightly doped region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 27)
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13. The method of claim wherein said act of forming said single lightly doped region is performed subsequent to formation of said gate structure, said act of forming said double lightly doped region is performed through said dielectric layer, and said act of forming said triple lightly doped region is performed subsequent to said act of narrowing said dielectric spacer.
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17. A method of forming a memory device including a memory array portion and a peripheral logic portion, comprising:
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forming at least one gate structure in an array portion of the device and at least one gate structure in a penphcry portion of the device, whereby each said gate structure controls charge carriers in a respective channel region of said substrate;
forming a single lightly doped region in said substrate on opposite sides of each said respective channel region;
forming a dielectric spacer having a first width adjacent opposite sides of each of said gate structures, wherein a portion of said single lightly doped region underlies said spacer;
forming a heavily-doped region in said substrate on opposite sides of said gate structure in said periphery portion;
removing a portion of said spacer from the sides of said gate structure such that said spacer has a second width smaller than said first width; and
forming a double lightly doped region in said substrate adjacent said single lightly doped region, wherein said double lightly doped region underlies a former position of said removed portion of said spacer. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A method of forming a semiconductor device, said method comprising:
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forming at least one gate structure on a substrate, said at least one gate structure defining at least one channel region residing below said at least one gate structure;
forming at least one single lightly doped region in said substrate adjacent said at least one channel region;
forming a dielectric spacer on at least one side of said at least one gate structure;
forming at least one heavily doped region in a portion of said substrate not covered by said dielectric spacer and adjacent said at least one single lightly doped region;
narrowing said dielectric spacer OD said at least one side of said at least one gate structure; and
forming at least one double lightly doped region in said substrate, adjacent said at least one channel region and said at least one single lightly doped region.
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Specification