Method of avoiding dielectric arcing
First Claim
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1. A method for reducing electrical charge imbalances in a semiconductor process wafer comprising the steps of:
- providing a semiconductor process wafer comprising a dielectric insulating layer;
exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and
, treating the semiconductor process wafer with a controlled atmosphere of treatment gas comprising one of a continuous and periodic flow of at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions.
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Abstract
A method for reducing electrical charge imbalances in a semiconductor process wafer including providing a semiconductor process wafer including a dielectric insulating layer; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and, treating the semiconductor process wafer with a controlled atmosphere of treatment gas including at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions.
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Citations
18 Claims
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1. A method for reducing electrical charge imbalances in a semiconductor process wafer comprising the steps of:
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providing a semiconductor process wafer comprising a dielectric insulating layer;
exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and
,treating the semiconductor process wafer with a controlled atmosphere of treatment gas comprising one of a continuous and periodic flow of at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for avoiding or reducing photo-induced electrical charge imbalances leading to electric discharge arcing comprising the steps of:
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providing a semiconductor process wafer comprising a dielectric insulating layer and an overlying resist layer for forming a lithographic pattern therein;
exposing the resist layer to an activating source of photons thereby forming electrical charge imbalances in the semiconductor process wafer; and
,controllably contacting the semiconductor process wafer with a treatment gas comprising one of a continuous and periodic flow of at least one of inert gas and hydrogen to at least partially neutralize the electrical charge imbalances. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification