Optical sensor and manufacturing method of the same
First Claim
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1. A method of manufacturing an integrated optical sensor having a P-type silicon substrate in which P-channel MOS transistors are formed in N-type well regions and N-channel MOS transistors are formed in P-type well regions, adjacent well regions being in contact with each other;
- and a semiconductor light-receiving element having an N-type region formed in the P-type silicon substrate to form a PN junction spaced apart from the N-type and P-type well regions, comprising the steps of;
implanting N-type impurities into the silicon substrate to simultaneously form the N-type well regions and the N-type region of the semiconductor light-receiving element;
selectively oxidizing the silicon substrate directly above the N-type well regions and the N-type region of the semiconductor light-receiving element;
forming a photoresist mask on and around the selectively formed oxide above the N-type region of the semiconductor light-receiving element; and
implanting P-type impurities into the silicon substrate to form the P-type well regions using the photoresist mask and the selectively formed oxide as masks.
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Abstract
A high-sensitive optical sensor is provided. In the optical sensor in which MOS transistors and a semiconductor light-receiving element are integrated, the light-receiving element includes a PN junction, and charges generated by the irradiation with light are accumulated at the PN junction, the PN junction of the light-receiving element is isolated from well regions of the MOS transistors.
4 Citations
1 Claim
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1. A method of manufacturing an integrated optical sensor having a P-type silicon substrate in which P-channel MOS transistors are formed in N-type well regions and N-channel MOS transistors are formed in P-type well regions, adjacent well regions being in contact with each other;
- and a semiconductor light-receiving element having an N-type region formed in the P-type silicon substrate to form a PN junction spaced apart from the N-type and P-type well regions, comprising the steps of;
implanting N-type impurities into the silicon substrate to simultaneously form the N-type well regions and the N-type region of the semiconductor light-receiving element;
selectively oxidizing the silicon substrate directly above the N-type well regions and the N-type region of the semiconductor light-receiving element;
forming a photoresist mask on and around the selectively formed oxide above the N-type region of the semiconductor light-receiving element; and
implanting P-type impurities into the silicon substrate to form the P-type well regions using the photoresist mask and the selectively formed oxide as masks.
- and a semiconductor light-receiving element having an N-type region formed in the P-type silicon substrate to form a PN junction spaced apart from the N-type and P-type well regions, comprising the steps of;
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Current AssigneeAblic Inc. (MinebeaMitsumi Inc.)
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Original AssigneeSeiko Instruments Incorporated (Seiko Group)
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InventorsOmi, Toshihiko
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Primary Examiner(s)GEBREMARIAM, SAMUEL A
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Application NumberUS10/005,036Publication NumberTime in Patent Office945 DaysField of Search257/292, 257/436, 257/462, 257/232, 438/48US Class Current257/292CPC Class CodesH01L 27/14609 Pixel-elements with integra...H01L 27/14689 MOS based technologies
