Input/output protection device for a semiconductor integrated circuit

• US 6,759,716 B1
• Filed: 07/19/2000
• Issued: 07/06/2004
• Est. Priority Date: 07/19/1999
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Morishita, Yasuyuki
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): NGUYEN, DILINH P
• Application Number:
  US09/619,669
• Time in Patent Office: 1,448 Days
• Field of Search: 257/174, 257/372, 257/173, 257/296, 257/170, 257/409, 257/484, 257/605, 257/355-363, 257/578, 257/591
• US Class Current: 257/357
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements

Abstract

An input/output protection device of lateral, bipolar type quickly responds to an excess voltage pulse and/or an excess current pulse of, for example, electrostatic discharge. In a region of a first conduction type (a fourth diffusion layer) of a semiconductor substrate, a first diffusion layer of a second conduction type opposite to the first conduction type is fabricated, the layer being connected to an input/output terminal. A second diffusion layer of the second conduction type is fabricated to be connected to electrode wiring at a fixed potential. A third diffusion layer of the second conduction type is manufactured at a bottom of the second diffusion layer and is connected to the second diffusion layer. The first diffusion layer is circularly enclosed with the third diffusion layer. When a high voltage is applied to the input/output terminal, a lateral, bipolar transistor including the first diffusion layer as a collector, the second and third diffusion layers as an emitter, and the region of the first conduction type or the fourth diffusion layer as a base is put to operation.

Claims

1. An input/output protection device for a semiconductor integrated circuit having a substrate of a first conduction type, an internal circuit, an input/output terminal, electrode wiring, and signal wiring, said protection device comprising:

a first region of a first diffusion layer fabricated in a region of the first conduction type of the semiconductor substrate, the first diffusion layer having a second conduction type opposite the first conduction type, said first region being connected to the input/output terminal;

a second region of said first diffusion layer of the second conduction type being hold at a predetermined potential; and

a third region having a diffusion layer of the second conduction type fabricated at a bottom of the second region, the third region being connected to the second region of said first diffusion layer, said third region being fabricated at a location other than at a bottom of said first diffusion layer of said first region,

the first region being circularly enclosed by the second and third regions, said first region, said second region, and said third region thereby forming a parasitic bipolar transistor in which said first region serves as a collector thereof and said second region and said third region serve as an emitter thereof.

2. An input/output protection device in accordance with claim 1, wherein the region of the first conduction type of the semiconductor substrate includes a fourth diffusion layer having an impurity concentration higher than that of the semiconductor substrate.

3. An input/output protection device in accordance with claim 2,

wherein the impurity concentration of the fourth diffusion layer monotonously decreases in a direction from a surface of the semiconductor substrate to an inner section thereof.

4. An input/output protection device in accordance with claim 3 wherein the third diffusion layer has a depth equal to or more than that of the fourth diffusion layer.

5. An input/output protection device in accordance with claim 3, wherein a lateral, bipolar transistor including the first diffusion layer as a collector, the second and third diffusion layers as an emitter, and the region of the first conduction type or the fourth diffusion layer as a base is put to operation.

6. An input/output protection device in accordance with claim 3, wherein the first and second diffusion layers are isolated from each other by a device separating isolation layer on a surface of the semiconductor substrate.

7. An input/output protection device in accordance with claim 2, wherein the third diffusion layer has a depth equal to or more than that of the fourth diffusion layer.

8. An input/output protection device in accordance with claim 7, wherein a lateral, bipolar transistor including the first diffusion layer as a collector, the second and third diffusion layers as an emitter, and the region of the first conduction type or the fourth diffusion layer as a base is put to operation.

9. An input/output protection device in accordance with claim 7, wherein the first and second diffusion layers are isolated from each other by a device separating isolation layer on a surface of the semiconductor substrate.

10. An input/output protection device in accordance with claim 2, wherein a lateral, bipolar transistor including the first diffusion layer as a collector, the second and third diffusion layers as an emitter, and the region of the first conduction type or the fourth diffusion layer as a base is put to operation.

11. An input/output protection device in accordance with claim 2, wherein the first and second diffusion layers are isolated from each other by a device separating isolation layer on a surface of the semiconductor substrate.

12. An input/output protection device in accordance with claim 1, wherein a lateral, bipolar transistor including the first diffusion layer as a collector, the second and third diffusion layers as an emitter, and the region of the first conduction type or the fourth diffusion layer as a base is put to operation.

13. An input/output protection device in accordance with claim 12, wherein the first and second diffusion layers are isolated from each other by a device separating isolation layer on a surface of the semiconductor substrate.

14. An input/output protection device in accordance with claim 1, wherein the first and second diffusion layers are isolated from each other by a device separating isolation layer on a surface of the semiconductor substrate.

15. An input/output protection device in accordance with claim 14, wherein the device separating isolation layer or the gate electrode is fabricated in a circular shape.

16. An input/output protection device in accordance with claim 1, wherein the first and second diffusion layers are maw re with a gate electrode disposed on a surface of the semiconductor substrate.

17. An input/output protection device in accordance with claim 16, wherein the gate electrode is connected to the signal wring of the internal circuit of the semiconductor integrated circuit.

18. An input/output protection device in accordance with claim 16, wherein the gate electrode is fixed to a predetermined potential.

19. An input/output protection device in accordance with claim 1, wherein:

the first conduction type is a p type and the second conduction type is an n type; and

the predetermined potential is a ground potential.

20. An input/output protection device in accordance with claims 1, wherein:

the first conduction type is an n type and the second conduction type is a p type; and

the predetermined potential is a potential of a power source.

21. The protection device of claim 1, wherein a protection of said internal circuit occurs by an avalanche breakdown in which said first diffusion layer connected to said input/output terminal serves as a collector and said second and third diffusion layers serve as an emitter for a lateral bipolar transistor.