Multi-chip package

• US 6,759,753 B2
• Filed: 05/21/2003
• Issued: 07/06/2004
• Est. Priority Date: 05/31/2002
• Status: Expired due to Fees

• Current Assignee: Gigno Technology Co., Ltd.
• Original Assignee: Gigno Technology Co., Ltd.
• Inventors: Chao, Yuan-Jen
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US10/442,281
• Publication Number:
  US 20030222342A1
• Time in Patent Office: 412 Days
• Field of Search: 257/723, 257/787, 257/780, 257/781, 257/784, 257/666
• US Class Current: 257/787
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19107 off-chip wires
• CPC Class Codes: H01L 2924/207 Diameter ranges

Abstract

A multi-chip package includes a transparent substrate, at least two chips, a plurality of connecting terminals, and a molding compound. In this case, the transparent substrate has a conductive layer for electrical inter-connection. The chips are mounted on the transparent substrate, so that the chips and the conductive layer form a circuitry system. At least one of the chips is provided on the transparent substrate by way of flip-chip attachment. The connecting terminals electrically connect to the circuitry system through a plurality of wires. Thus, the circuitry system electrically connects to external devices with the wires and connecting terminals. The molding compound at least encapsulates the wires.

Claims

1. A multi-chip package, comprising:

a transparent substrate having a conductive layer for electrical inter-connection;

at least two chips mounted on the transparent substrate, wherein the chips and the conductive layer form a circuitry system and at least one of the chips is provided on the transparent substrate by a flip-chip attachment in order to permit visual inspection of the at least one chip;

a plurality of connecting terminals for electrically connecting to the circuitry system through a plurality of wires, the connecting terminals electrically connecting the circuitry system outwardly; and

a molding compound for at least encapsulating the wires.

2. The multi-chip package of claim 1, further comprising:

a pad, which is provided at one side of the transparent substrate for carrying the transparent substrate.

3. The multi-chip package of claim 1, wherein the transparent substrate is a glass substrate.

4. The multi-chip package of claim 1, wherein the molding compound further encapsulates the chips.

5. The multi-chip package of claim 1, wherein the molding compound further encapsulates the transparent substrate.

6. The multi-chip package of claim 1, wherein the molding compound further encapsulates at least a part of the connecting terminals.

7. The multi-chip package of claim 1, wherein the chip provided by way of the flip-chip attachment utilizes an optical signal to communicate outwardly through the transparent substrate.

8. The multi-chip package of claim 1, wherein at least one of the chips is provided by way of a wire bonding process.

9. The multi-chip package of claim 1, wherein at least one of the connecting terminals is electrically connected to the conductive layer of the circuitry system via the wires for electrically connecting the circuitry system outwardly.

10. The multi-chip package of claim 1, wherein at least one of the connecting terminals is electrically connected to at least one of the chips via the wires for electrically connecting the circuitry system outwardly.