System and method for non-contact electrical testing employing a CAM derived reference

• US 6,759,850 B2
• Filed: 03/27/2002
• Issued: 07/06/2004
• Est. Priority Date: 03/28/2001
• Status: Expired due to Fees

• Current Assignee: Orbotech Limited (KLA Corporation)
• Original Assignee: Orbotech Limited (KLA Corporation)
• Inventors: Haran, On, Roikhel, Boris, Harzanu, Benyamin
• Primary Examiner(s): Deb, Anjan K.
• Application Number:
  US10/106,254
• Publication Number:
  US 20030011380A1
• Time in Patent Office: 832 Days
• Field of Search: 324/522, 324/529-531, 324/537, 324/750, 324/260, 324/658, 703/2-6
• US Class Current: 324/522
• CPC Class Codes: G01R 31/304 of printed or hybrid circuits G01R31/305 - G01R31/315 take precedence

Abstract

A system and method for electrically testing electrical circuits in which electromagnetic values that are to be sensed by an array of sensors are forecast or simulated, for use as a reference, by calculation using computer files corresponding to a board under test and to an array of sensors.

Claims

1. A tester for electrically testing a board under test (BUT) for defects, comprising:

a sensor operative to provide detection outputs corresponding to a sensed electrical characteristic for selected locations on a BUT; and

a defect processor configured to receive;

said detection outputs, and

a reference representing anticipated values corresponding to the detection outputs for the selected BUT locations, said reference including anticipated values that are calculated from information representing said BUT and that take into account an electric effect of said sensor; and

said defect processor being operative to output an indication of a possible electrical defect in said BUT by comparing said detection outputs to said reference anticipated values.

2. The tester claimed in claim 1, wherein said BUT is a printed circuit board.

3. The tester claimed in claim 1, wherein said BUT is electrically stimulated prior to detection by said sensor.

4. The tester claimed in claim 1, wherein said sensor senses said BUT without coming into physical contact with said BUT.

5. The tester claimed in claim 1, wherein said sensed electrical characteristic is electrical current.

6. The tester claimed in claim 1, wherein said reference includes anticipated values calculated from a plurality of CAM files.

7. The tester claimed in claim 6, wherein said anticipated values are calculated from a computer file, wherein said computer file comprises a three dimensional model of said sensor.

8. The tester claimed in claim 1, wherein said reference includes anticipated values calculated from a computer file representing said sensor and from a CAM file representing a structure of the BUT, and wherein a first portion of said anticipated values is calculated when said CAM file is in a first spatial orientation relative to said computer file, and a second portion of said anticipated values is calculated when said CAM file is in a second spatial orientation relative to said computer file.

9. The tester claimed in claim 1, wherein an anticipated value is determined from a capacitance matrix calculated for selected conductive elements affecting said sensor.

10. The tester claimed in claim 9, wherein said capacitance matrix is calculated based on an assumption that a charge distribution for said selected conductive elements behaves according to a predetermined function.

11. The tester claimed in claim 10, wherein said predetermined charge distribution function is uniform for each selected conductive element.

12. A tester for electrically testing a board under test (BUT) for defects, comprising:

a sensor operative to provide a detection output, said detection output including a sensed electrical characteristic for selected locations on a BUT; and

a defect processor configured to receive;

said detection output, and

a reference representing anticipated values corresponding to an electrical characteristic to be sensed by said sensor at selected locations on the BUT, said reference including anticipated values calculated from at least one computerized CAM file representing a three dimensional model of said BUT and said sensor, and

said defect processor being operative to output an indication of a possible electrical defect in said BUT in response to comparing said detection output to said reference.

13. The tester claimed in claim 12, wherein said BUT is a printed circuit board.

14. The tester claimed in claim 12, wherein each of the selected locations on said BUT is electrically stimulated while being sensed by said sensor.

15. The tester claimed in claim 12, wherein said sensed electrical characteristic is electrical current.

16. The tester claimed in claim 12, wherein said computer file further includes a net list representing nets on said BUT.

17. The tester claimed in claim 12, wherein anticipated values are calculated from said computerized CAM file, said computerized CAM file representing said BUT and including a three dimensional model of said sensor.

18. The tester claimed in claim 12, wherein an anticipated value is determined from a capacitance matrix calculated for selected conductive elements affecting said sensor, when said CAM file and said computer file are arranged to represent a predetermined spatial orientation between said BUT and said sensor.

19. The tester claimed in claim 18, wherein said capacitance matrix is calculated based on an assumption that a charge distribution for said selected conductive elements on the BUT acts according to a predetermined function.

20. The tester claimed in claim 19, wherein said predetermined charge distribution function is uniform for each selected conductive element.

21. The tester claimed in claim 12, wherein an anticipated value is determined from summing the affects of capacitance between nets having a given voltage, said capacitance calculated from a model including a CAM file and a computer file that are arranged to represent a predetermined spatial orientation between said BUT and said sensor.

22. A method for electrically testing a board under test (BUT) for defects, comprising:

sensing a BUT with a sensor at a multiplicity of selected locations;

outputting sensed values indicating an electrical characteristic sensed at the selected locations;

comparing said sensed values to corresponding anticipated values, said anticipated values being calculated from a CAM file representing said BUT and information representing said sensor, said calculated values being calculated to take into account an electric effect of said sensor; and

determining a defect in said BUT in response to said comparing.

23. The method claimed in claim 22, wherein said comparing comprises comparing anticipated values that are calculated from said CAM file and from said information according to at least one spatial orientation between said BUT and said sensor.

24. The method claimed in claim 22, wherein said comparing comprises comparing an anticipated value that is determined from a capacitance matrix calculated for selected conductive elements affecting said sensor.

25. The method claimed in claim 24, wherein said comparing comprises comparing an anticipated value determined from a capacitance matrix that is calculated based on an assumption that a charge distribution for said selected conductive elements acts according to a predetermined function.

26. The method claimed in claim 25, wherein said predetermined function is a uniform distribution of charge.

27. The method claimed in claim 22, wherein said comparing comprises comparing a sensed value of current to an anticipated value of current that is calculated as a function of capacitance between selected nets on said BUT.

28. A method for electrically testing a board under test (BUT) for defects, comprising:

sensing a BUT with a sensor at a multiplicity of locations;

outputting sensed values indicating an electrical characteristic sensed by said sensor at selected locations;

comparing said sensed values to corresponding anticipated values, said anticipated values including values that are calculated from at least one computer file representing a three dimensional model of said BUT and said sensor; and

determining a defect in said BUT in accordance with said comparison.

29. The method claimed in claim 28, wherein said comparing comprises comparing anticipated values that are calculated from at least one CAM file representing said BUT and at least one computer file representing said sensor.

30. The method claimed in claim 28, wherein said comparing comprises comparing an anticipated value that is determined from a capacitance matrix calculated for selected conductive elements affecting said sensor.

31. The method claimed in claim 30, wherein said comparing comprises comparing an anticipated value that is determined from a capacitance matrix that is calculated based on an assumption that a charge distribution for said selected conductive elements acts according to a predetermined function.

32. The method claimed in claim 31, wherein said predetermined function is a uniform distribution of charge.

33. The method claimed in claim 28, wherein said comparing comprises comparing a sensed value of current to an anticipated value of current that is calculated as a function of capacitance between selected nets on said BUT.

34. A method for calculating a reference map representing a BUT for use in an electrical tester having a plurality of sensors, comprising:

calculating an electrical charge for selected conductive portions of a BUT using at least one computer file representing said BUT;

calculating an electrical charge for selected sensors using a computer file representing said sensors;

calculating electromagnetic values affected by selected conductive portions using the calculated electrical charge for said conductive portions of said BUT and the calculated electrical charge for said selected sensors, said electromagnetic values taking into account an electric effect of said selected sensors; and

collecting the calculated electromagnetic values into a reference map.

35. A method for-calculating a reference map representing a BUT for use in an electrical tester having at least one sensor, comprising:

(a) identifying various conductive portions on a BUT;

(b) calculating a capacitance between a selected sensor and a selected conductive portion on the BUT;

(c) multiplying said capacitance by a voltage;

(d) summing the result of the multiplication in (c) with respect to a selected sensor for each of a plurality of selected conductive portions on the BUT, and multiplying said sum with a current phase to determine a value for current; and

(e) collecting a plurality of current values calculated in (d) to form a reference map representing a BUT.

36. The method claimed in claim 35 and wherein operation (b) further comprises:

calculating a capacitance between a selected sensor and another sensor.

37. The method claimed in claim 36 and further comprising changing a spatial orientation between a computer file representing said BUT and a computer file representing said sensor.

38. The method claimed in claim 35 and further comprising changing a spatial orientation between a computer file representing said BUT and a computer file representing said sensor.