Line segmentation in programmable logic devices having redundancy circuitry

• US 6,759,871 B2
• Filed: 04/22/2003
• Issued: 07/06/2004
• Est. Priority Date: 04/26/2000
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Zhang, Changsong, Nguyen, Triet, Jefferson, David
• Primary Examiner(s): LE, DON P
• Application Number:
  US10/422,007
• Publication Number:
  US 20030201793A1
• Time in Patent Office: 441 Days
• Field of Search: 326/37-41, 326/82, 326/83, 326/88
• US Class Current: 326/41
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.

Claims

1. A programmable logic device comprising:

a first plurality of logic array blocks, the first plurality of logic array blocks comprising a first logic array block and a second logic array block;

a first programmable interconnect line coupled to a first terminal of a segmentation buffer and programmably coupled to the first logic array block;

a second programmable interconnect line coupled to a second terminal of the segmentation buffer and programmably coupled to the second logic array block;

a second plurality of logic array blocks, wherein the second plurality of logic array blocks are redundant; and

a logic circuit coupled to the segmentation buffer, wherein the logic circuit receives a signal, the signal at a first logic level if the first logic array block is defective.

2. The integrated circuit of claim 1 wherein if the first logic array block is initially configured to drive a signal on the first programmable interconnect line and the first logic array block is defective, then a configuration of the first logic array block is moved to the second logic array block and the segmentation buffer is configured to drive a signal on the second programmable interconnect line to the first programmable interconnect line.

3. The programmable logic device of claim 1 wherein if the segmentation buffer is originally configured to drive a signal on the first programmable interconnect line to the second programmable interconnect line and the first logic array block is defective, the segmentation buffer is reconfigured to drive a signal on the second programmable interconnect line to the first programmable interconnect line.

4. The programmable logic device of claim 1 wherein if the segmentation buffer is originally configured to provide a high impedance between the first programmable interconnect line and the second programmable interconnect line and the fist logic array block is originally configured to provide a signal to the first programmable interconnect line, and the first logic array block is defective, the segmentation buffer is reconfigured to drive a signal from the second programmable interconnect line to the first programmable interconnect line.

5. The programmable logic device of claim 1 wherein if the segmentation buffer is originally configured to provide a high impedance between the first programmable interconnect line and the second programmable interconnect line and the fist logic array block is originally configured to receive a signal from the first programmable interconnect line, and the first logic array block is defective, the segmentation buffer is reconfigured to drive a signal from the first programmable interconnect line to the second programmable interconnect line.

6. An integrated circuit comprising the programmable logic device of claim 1.

7. An integrated circuit comprising:

a plurality of logic blocks comprising a first logic block, a second logic block, and a third logic block;

a plurality of configurable buffers including a first configurable buffer and a second configurable buffer;

a first interconnect line programmably coupled to the first logic block and coupled to the first configurable buffer;

a second interconnect line programmably coupled to the second logic block and coupled to the first configurable buffer and the second configurable buffer;

a third interconnect line programmably coupled to the third logic block and coupled to the second configurable buffer, and

a logic circuit coupled to the first configurable buffer and the second configurable buffer,

wherein the logic circuit receives an first configuration signal and a signal identifying the location of a defective logic block, and provides a second configuration signal to the first configurable buffer and a third configuration signal to the second configurable buffer.

8. The integrated circuit of claim 7 wherein the first configurable buffer is capable of being initially configured to buffer a signal on the first interconnect line to the second interconnect line, to buffer a signal on the second interconnect line to the first interconnect line, or to disconnect the first interconnect line from the second interconnect line.

9. The integrated circuit of claim 8 wherein if the segmentation buffer is originally configured to buffer a signal on the first interconnect line to the second interconnect line and the first logic array block is defective, the segmentation buffer is reconfigured to buffer a signal on the second interconnect line to the first interconnect line.

10. The integrated circuit of claim 8 wherein the first logic block is initially configured, and if the first block is defective, the configuration of the first logic block is moved to the second logic block.

11. An integrated circuit comprising:

a first plurality of logic blocks, the first plurality of logic blocks comprising a first logic block and a second logic block;

a first programmable interconnect line coupled to a first terminal of a segmentation buffer and programmably coupled to the first logic block;

a second programmable interconnect line coupled to a second terminal of the segmentation buffer and programmably coupled to the second logic block; and

a logic circuit coupled to the segmentation buffer, wherein the logic circuit receives a signal, the signal having a first polarity if the first logic block is nonfunctional, and

wherein if the first logic block is initially configured to drive a signal on the first programmable interconnect line, the segmentation buffer is capable of being initially configured by the logic circuit to provide an open circuit between the first programmable interconnect line and the second programmable interconnect line or as a buffer driving the signal on the first programmable interconnect line to the second programmable interconnect line.

12. The integrated circuit of claim 11 wherein if the first logic block is initially configured to drive a signal on the first programmable interconnect line and the first logic block is defective, then a configuration of the first logic block is moved to the second logic block and the segmentation buffer is configured to drive a signal on the second programmable interconnect line to the first programmable interconnect line.

13. The integrated circuit of claim 11 wherein if the segmentation buffer is originally configured to provide a high impedance between the first programmable interconnect line and the second programmable interconnect line and the fist logic block is originally configured to provide a signal to the first programmable interconnect line, and the first logic block is defective, the segmentation buffer is reconfigured to drive a signal from the second programmable interconnect line to the first programmable interconnect line.

14. A method of segmenting a programmable interconnect line in an integrated circuit comprising a first logic block, a second logic block, a configurable buffer disposed between the first logic block and the second logic block, a first programmable interconnect line segment coupled to the first logic block and the configurable buffer, and a second programmable interconnect line segment coupled to the configurable buffer and the second logic block, the method comprising:

programming an initial configuration for the configurable buffer and an initial configuration for the first logic block into the integrated circuit;

determining if the first logic block is defective; and

if the first logic block is defective, the first logic block was initially configured to provide a signal on the first programmable interconnect line segment, and the configurable buffer was configured to receive the signal on the first programmable interconnect line segment and provide an output to the second programmable interconnect line segment,

then setting the configuration of the configurable buffer to receive a signal on the second programmable interconnect line segment and provide an output to the first programmable interconnect line segment.

15. The method of claim 14 wherein when the first logic block is configured to provide a signal to the first programmable interconnect line segment, the configurable buffer is capable of being configured to provide an open circuit between the first programmable interconnect line segment and the second programmable interconnect line segment or to receive the signal on the first programmable interconnect line segment and provide an output to the second programmable interconnect line segment, and

when the second logic block is configured to provide a signal to the second programmable interconnect line segment, the configurable buffer is capable of being configured to provide an open circuit between the first programmable interconnect line segment and the second programmable interconnect line segment or to receive the signal on the second programmable interconnect line segment an provide an output to the first programmable interconnect line segment.

16. The method of claim 15 further comprising a redundant logic block disposed in a first direction from the first logic block, the configurable buffer, and the second logic block,

wherein if the first logic block is defective, the initial configuration of the first logic block is moved to the second logic block.

17. A method of segmenting a programmable interconnect line in an integrated circuit comprising a first logic block, a first configurable buffer disposed in a first direction from the first logic block, a second logic block disposed in the first direction from the first configurable buffer, a second configurable buffer disposed in the first direction from the second logic block, a third logic block disposed in the first direction from the second configurable buffer, a first programmable interconnect line segment coupled to the first logic block and the first configurable buffer, a second programmable interconnect line segment coupled to the first configurable buffer, the second logic block, and the second configurable buffer, and a third programmable interconnect line segment coupled to the second configurable buffer and the third logic block, wherein the second configurable buffer is initially configured to couple the second programmable interconnect line segment and the third programmable interconnect line segment, the method comprising:

programming an initial configuration for the first configurable buffer and an initial configuration for the first logic block into the integrated circuit;

determining if the first logic block is defective; and

if the first logic block is defective, the first logic block was initially configured to provide a signal to the first programmable interconnect line segment, and the first configurable buffer was initially configured to disconnect the first programmable interconnect line segment from the second programmable interconnect line segment,

then setting the configuration of the first configurable buffer such that it is configured to receive a signal on the second programmable interconnect line segment and provide an output to the first programmable interconnect line segment, and setting the configuration of the second configurable buffer such that it is configured to disconnect the second programmable interconnect line segment from the third programmable interconnect line segment.

18. The method of claim 17 further comprising:

if the first logic block is defective, the first logic was initially configured to provide a signal to the first programmable interconnect line segment, and the first configurable buffer was initially configured to receive the signal from the first programmable interconnect line segment and to provide an output to the second programmable interconnect line segment,

then setting the configuration of the first configurable buffer such that it is configured to receive a signal from the second programmable interconnect line segment and provide an output to the first programmable interconnect line segment.

19. The method of claim 17 wherein when the first logic block is configured to provide a signal to the first programmable interconnect line segment, the configurable buffer is capable of being configured to disconnect the first programmable interconnect line segment from the second programmable interconnect line segment or to receive the signal on the first programmable interconnect line segment and provide an output to the second programmable interconnect line segment, and

when the second logic block is configured to provide a signal to the second programmable interconnect line segment, the configurable buffer is capable of being configured to disconnect the first programmable interconnect line segment from the second programmable interconnect line segment or to receive the signal on the second programmable interconnect line segment and provide an output to the first programmable interconnect line segment.

20. The method of claim 19 further comprising a redundant logic block disposed in a first direction from the first logic block, the configurable buffer, and the second logic block,

wherein if the first logic block is defective, the initial configuration of the first logic block is moved to the second logic block.