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Line segmentation in programmable logic devices having redundancy circuitry

  • US 6,759,871 B2
  • Filed: 04/22/2003
  • Issued: 07/06/2004
  • Est. Priority Date: 04/26/2000
  • Status: Expired due to Term
First Claim
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1. A programmable logic device comprising:

  • a first plurality of logic array blocks, the first plurality of logic array blocks comprising a first logic array block and a second logic array block;

    a first programmable interconnect line coupled to a first terminal of a segmentation buffer and programmably coupled to the first logic array block;

    a second programmable interconnect line coupled to a second terminal of the segmentation buffer and programmably coupled to the second logic array block;

    a second plurality of logic array blocks, wherein the second plurality of logic array blocks are redundant; and

    a logic circuit coupled to the segmentation buffer, wherein the logic circuit receives a signal, the signal at a first logic level if the first logic array block is defective.

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