Large gain range, high linearity, low noise MOS VGA

• US 6,759,904 B2
• Filed: 06/28/2002
• Issued: 07/06/2004
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Behzad, Arya R.
• Primary Examiner(s): NGUYEN, KHANH V
• Application Number:
  US10/183,552
• Publication Number:
  US 20030020544A1
• Time in Patent Office: 739 Days
• Field of Search: 330/254, 327/359
• US Class Current: 330/254
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0026 Multilayer LC-filter
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03B 2201/0266 the means comprising a transistor
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03J 1/0075 where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 1/023 : by using voltage variable capacitance diodes
• CPC Class Codes: H03L 7/10 : for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/104 : using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their V_ds dynamically modified in conjunction with current steering of the differential pairs sources.

Claims

1. An integrated MOS VGA, comprising:

a substrate;

a first differential pair amplifier disposed upon the substrate and coupled to a VGA output having a gain contributing to VGA gain in direct proportion to the first differential pair amplifier gain;

a second differential pair amplifier disposed upon the substrate and coupled to a VGA output having a gain, and coupled to the first differential amplifier such that an increase in second differential pair amplifier gain contributes to a decrease in the VGA gain; and

a variable voltage source coupled to the VGA output, a voltage output of the variable voltage source determining respective drain voltages on the first differential pair and the second differential pair based on a differential input signal received at the first differential pair amplifier and the second differential pair amplifier, and thereby controlling the gain of the first differential pair and the gain of the second differential pair.

2. The integrated MOS VGA of claim 1, wherein the variable voltage source controls the transconductance of the first and the second differential pair amplifiers.

3. The integrated MOS VGA of claim 1, wherein the variable voltage source is configured such that the voltage output of the variable voltage source is decreased for a large input signal, thereby decreasing the VGA gain while increasing linearity and reducing output distortion.

4. The integrated MOS VGA of claim 1, wherein the variable voltage source is configured such that the voltage output of the variable voltage source is increased for a small input signal, causing at least one transistor of the first and the second differential pair amplifiers to become biased in an active region, thereby increasing the VGA gain and reducing output distortion.

5. The integrated MOS VGA of claim 1, further comprising:

a control signal applied to the variable voltage source to control the voltage output of the variable voltage source.

6. The integrated MOS VGA of claim 1, wherein the variable voltage source is configured such that the VGA gain will never become zero.

7. An integrated MOS VGA, comprising:

a substrate;

a first transistor disposed upon the substrate, the first transistor having a first transistor gate, a first transistor source, and a first transistor drain, a first transistor drain-source V_ds voltage being provided across the first transistor source and the first transistor drain;

a second transistor disposed upon the substrate, the second transistor having a second transistor gate, a second transistor source, and a second transistor drain, a second transistor drain-source V_ds voltage being provided across the second transistor source and the second transistor drain;

a third transistor disposed upon the substrate, the third transistor having a third transistor gate, a third transistor source, and a third transistor drain, a third transistor drain-source V_ds voltage being provided across the third transistor source and the third transistor drain;

a fourth transistor disposed upon the substrate, the fourth transistor having a fourth transistor gate, a fourth transistor source, and a fourth transistor drain, a fourth transistor drain-source V_ds voltage being provided across the fourth transistor source and the fourth transistor drain;

the first transistor gate and the fourth transistor gate being responsive to a first input voltage, the second transistor gate and the third transistor gate being responsive to a second input voltage, the first transistor source being coupled to the second transistor source, the third transistor source being coupled to the fourth transistor source, the second transistor drain being coupled to the fourth transistor drain and the first transistor drain being coupled to the third transistor drain to provide a VGA output; and

a variable voltage source coupled to the VGA output, a voltage output of the variable voltage source determining respective drain-source V_ds voltages on the first, second, third, and fourth transistors based on a differential input received at the respective gates of the first, second, third, and fourth transistors, thereby controlling a transconductance of each of the first, second, third, and fourth transistors;

wherein the first transistor and the second transistor form a first differential pair amplifier with a gain, and the third transistor and the fourth transistor form a second differential pair amplifier with a gain; and

wherein an increase in the first differential pair gain contributes to an increase in VGA gain, and an increase in the second differential pair amplifier gain contributes to a decrease in the VGA gain.

8. The integrated MOS VGA of claim 7, wherein the variable voltage source is configured such that the voltage output of the variable voltage source is decreased for a large input signal, thereby decreasing the VGA gain while increasing linearity and reducing output distortion.

9. The integrated MOS VGA of claim 7, wherein the variable voltage source is configured such that the voltage output of the variable voltage source is increased for a small input signal, causing at least one of the first, second, third, and fourth transistors to become biased in an active region, thereby increasing the VGA gain and reducing output distortion.

10. The integrated MOS VGA of claim 7, further comprising:

a control signal applied to the variable voltage source to control the voltage output of the variable voltage source.

11. A method for providing, over a wide range of input signal voltages, variable gain amplification having a linear change in output current gain at a differential current output port as a function of a change in differential voltage input at a differential voltage input port, comprising the steps of:

providing a variable gain amplifier responsive to the differential voltage input, the variable gain amplifier having

a first common source differential pair amplifier having output drains; and

a second common source differential pair amplifier having output drains;

wherein the first common source differential pair output drains and the second common source differential pair output drains are connected in parallel to form the differential current output port and are responsive to the differential voltage input to provide the output current gain at the differential current output port; and

adjusting first common source differential pair amplifier drain-source V_ds voltages and second common source differential pair amplifier drain-source V_ds voltages as the differential voltage input changes.

12. The method of claim 11, wherein the step of adjusting includes the step of reducing the first common source differential pair amplifier drain-source V_ds voltages and the second common source differential pair amplifier drain-source V_ds voltages as the differential voltage input increases.

13. The method of claim 11, wherein the step of adjusting includes the step of increasing the first common source differential pair amplifier drain-source V_ds voltages and the second common source differential pair amplifier drain-source V_ds voltages as the differential voltage input decreases.

14. The method of claim 11, wherein the step of adjusting includes the step of changing absolute direct current voltage at the differential current output port.

15. The method of claim 14, wherein the step of changing absolute direct current voltage includes the steps of:

coupling a voltage control source across the differential current output port; and

inputting a gain control signal derived from an input control voltage signal to control the voltage control source to change the absolute direct current voltage at the differential current output port as the differential input voltage changes.