Oscillator circuit

• US 6,759,914 B2
• Filed: 10/25/2002
• Issued: 07/06/2004
• Est. Priority Date: 05/12/2000
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Rusznyak, Andreas
• Primary Examiner(s): Mis, David
• Application Number:
  US10/258,725
• Publication Number:
  US 20030107445A1
• Time in Patent Office: 620 Days
• Field of Search: 331/116.R, 331/116.FE, 331/117.R, 331/117.FE, 331/117.D, 331/158, 331/175, 331/185, 331/186
• US Class Current: 331/116.0FE
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence

Abstract

An oscillator circuit (300) comprising: a resonator (Q) connected between an input (IN)and an output (OUT); an inverter having first and second driver transistors (MP, MN) connected in series via an output-coupled node; first and second biasing transistors (MPD, MND) for biasing the driver transistors; and first and second limiting means between the gate electrodes of the driver transistors respectively and the output. The CMOS circuit allows regulation of the oscillation amplitude without need for well-controlled DC current sources to polarize correctly the driver transistors, and without need for a start-up circuit to ensure that both driver transistors remain in saturation when the circuit is powered on. A simple oscillator circuit (600) has an inverter whose input is capacitively coupled to the input (IN), first limiting means coupled between the inverter input and the output (OUT), and second limiting means coupled between the input (IN) and the output (OUT).

Claims

1. An oscillator circuit comprising:

an input and an output arranged for connection of a resonator therebetween;

inverter means having a first driver transistor and a second driver transistor coupled in series via said output;

biasing means having a first biasing element coupled between said output and a control electrode of the first driver transistor for biasing the first driver transistor, and a second biasing element coupled between said output and the control electrode of the second driver transistor for biasing the second driver transistor;

first limiting means coupled between the control electrode of said first driver transistor and a first node for receiving a signal representative of the signal at the output, and second limiting means coupled between the control electrode of said second driver transistor and a second node for receiving a signal representative of the signal at the output,

the control inputs of the first and second driver transistors being capacitively coupled to the input.

2. An oscillator circuit according to claim 1 further comprising amplifier means having an input coupled to the output and having an output coupled to the nodes for receiving a signal representative of the signal at the output.

3. An oscillator circuit according to claim 1 further comprising:

first capacitive means coupled between the output and said first node for receiving a signal representative of the signal at the output;

first current defining means for defining the current flowing in the first limiting means;

second capacitive means coupled between the output and said second node for receiving a signal representative of the signal at the output; and

second current defining means for defining the current flowing in the second limiting means.

4. An oscillator circuit according to claim 3 wherein the first current defining means comprises a diode-connected transistor and a capacitor between the first node for receiving a signal representative of the signal at the output and a first supply node, and the second current defining means comprises a diode-connected transistor and a capacitor between the second node for receiving a signal representative of the signal at the output and a second supply node.

5. An oscillator circuit according to claim 1, wherein the biasing means comprises resistive transistors having control electrodes.

6. An oscillator circuit according to claim 5 wherein the control electrodes of the resistive transistors of the first and second biasing means are respectively coupled to the second and first supply nodes.

7. An oscillator circuit according to claim 5 wherein the control electrodes of the resistive transistors are coupled to means for providing control voltages for ensuring that the resistive transistors conduct when the voltage on the control electrodes of the driver transistors is less than a start-up voltage on the output.

8. An oscillator circuit according to claim 7 wherein the means for providing control voltages comprises:

means for providing a voltage representative of the start-up voltage and voltages representative of the threshold voltages of the biasing means, and means for generating therefrom the control voltages.

9. An oscillator circuit according to claim 1, further comprising a resistive transmission gate coupled between the input and the output to define the voltage on the input at low frequencies.

10. An oscillator circuit according to claim 9 wherein the resistive transmission gate has control electrodes which are coupled respectively to the first and second supply nodes.

11. An oscillator circuit comprising:

an input and an output arranged for connection of a resonator therebetween;

inverter means having an input and having an output coupled to the output of the circuit;

capacitance means coupled between the input of the circuit and the input of the inverter;

first limiting means coupled between the input of the inverter and the output of the circuit; and

second limiting means coupled between the input of the circuit and the output of the circuit.

12. An oscillator circuit according to claim 11 wherein

the inverter comprises first and second series-connected transistors,

the capacitance means comprises first and second capacitances coupled between the input of the circuit and the control electrodes of the first and second transistors respectively, and

the first limiting means comprises first and second transistors coupled between the output of the circuit and the control electrodes of the first and second transistors respectively.

13. An oscillator circuit according to claim 12, wherein the transistors are CMOS transistors.