Method of writing ferroelectric field effect transistor

• US 6,760,246 B1
• Filed: 05/01/2002
• Issued: 07/06/2004
• Est. Priority Date: 05/01/2002
• Status: Expired due to Fees

• Current Assignee: Celis Semiconductor Corp.
• Original Assignee: Celis Semiconductor Corp.
• Inventors: Kamp, David A., DeVilbiss, Alan D.
• Primary Examiner(s): HO, HOAI V
• Application Number:
  US10/136,210
• Time in Patent Office: 797 Days
• Field of Search: 365/145, 365/65
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A ferroelectric field effect transistor (FET) has a gate, source, drain, and substrate. A negative voltage is applied to the gate. Ground potential is applied to the source, drain, and substrate. The negative voltage has a magnitude at least equal to the coercive voltage of the FET. A positive voltage is then applied to the gate. Ground potential is applied to the source and substrate. The positive voltage is no less than the coercive voltage. Either a positive voltage or a ground potential is applied to the drain to write a logic state to the FET. A voltage is applied to the gate. Ground potential is applied to the source. A positive voltage is applied to the drain. The drain current is measured and compared to a compare current. The relative size of the drain current compared to the compare current is indicative of the stored logic state in the FET.

Claims

1. A method for interacting with a ferroelectric field effect transistor (FET) exhibiting hysteresis having a gate, source, drain, and substrate, the method comprising:

(a) applying a negative voltage to the gate and ground potential to the source, drain, and substrate, the negative voltage having a magnitude at least equal to a coercive voltage of the FET;

(b) applying a positive voltage to the gate and ground potential to the source and the substrate, the positive voltage having a magnitude at least equal to the coercive voltage; and

(c) selectively applying either a positive voltage or a ground potential to the drain to write a logic state to the FET, the positive voltage about equal to the positive voltage applied to the gate.

2. The method of claim 1 further including:

(a) applying a voltage to the gate, ground potential to the source, and a positive voltage to the drain, the voltage applied to the gate less than the coercive voltage and at least equal to the voltage applied to the drain;

(b) measuring the drain current through the drain; and

(c) comparing the drain current to a compare current, the drain current being larger or smaller than the compare current indicative of a stored logic state in the FET.

3. The method of claim 2 wherein the compare current has a magnitude between a magnitude of the drain current resulting when a positive voltage is applied to the drain and a magnitude of the drain current resulting when ground potential is applied to the drain.

4. A method for interacting with a selected ferroelectric field effect transistor (FET) in an array of ferroelectric FETs, each ferroelectric FET in the array having a gate, source, drain, substrate, and ferroelectric layer, the array arranged in rows and columns, the gate of each ferroelectric FETs in the same row coupled to a word line, the source of each ferroelectric FETs in the same row coupled to a source line, the drain of each ferroelectric FETs in the same column coupled to a bit line, the method comprising:

(a) applying a negative voltage to the word line of the selected FET and ground potential to the source line, bit line, and substrate of the selected FET, the negative voltage having a magnitude at least equal to a coercive voltage of the FET;

(b) applying a positive voltage to the word line of the selected FET and ground potential to the source line and the substrate of the selected FET, the positive voltage having a magnitude at least equal to the coercive voltage; and

(c) selectively applying either a positive voltage or a ground potential to the bit line of the selected FET to write a logic state to the selected FET, the positive voltage having a magnitude about equal to the magnitude of the positive voltage applied to the word line.

5. The method of claim 4 further comprising:

(a) applying a voltage to the word line of the selected FET, ground potential to the source line and the substrate of the selected FET, and a positive voltage to the bit line of the selected FET, the voltage applied to the word line of the selected FET less than the coercive voltage and at least equal to the voltage applied to the bit line of the selected FET;

(b) measuring the bit current of the bit line of the selected FET; and

(c) comparing the bit line current to a compare current, the bit line current being larger or smaller than the compare current indicative of a stored logic state in the selected FET.

6. The method of claim 4 further comprising:

(a) applying a voltage to the word line of the selected FET, ground potential to the source line and the substrate of the selected FET, and a positive voltage to the bit line of the selected FET, the voltage applied to the word line of the selected FET less than the coercive voltage and at least equal to the voltage applied to the bit line of the selected FET;

(b) measuring the bit voltage of the bit line of the selected FET; and

(c) comparing the bit line voltage to a compare voltage, the bit line voltage being larger or smaller than the compare voltage indicative of a stored logic state in the selected FET.

7. The method of claim 5 wherein the compare current has a magnitude between a magnitude of the drain current resulting when a positive voltage is applied to the bit line and a magnitude of the drain current resulting when ground potential is applied to the bit line.

8. A method as in claim 5 wherein each bit line of the array has an associated column latch and further comprising saving the logic state of the FET in the associated column latch of the bit line of the selected FET.

9. A method of interacting with a ferroelectric field effect transistor (FET) having a gate, source, drain, substrate, and a ferroelectric layer, the method comprising:

(a) applying a negative voltage to the gate and ground potential to the source, drain, and substrate, the negative voltage having a magnitude at least equal to a coercive voltage of the FET, and

(b) applying a positive voltage to the gate, ground potential to the substrate and the source, the positive voltage applied to the gate at least equal to a coercive voltage of the FET; and

(c) selectively applying either a positive voltage or ground potential to the drain to write a logic state to the FET, the positive voltage about equal to the positive voltage applied to the gate.

10. The method of claim 9 further including:

(a) applying a voltage to the gate, ground potential to the source, and a positive voltage to the drain, the voltage applied to the gate less than the coercive voltage and at least equal to the voltage applied to the drain;

(b) measuring the drain current through the drain; and

(c) comparing the drain current to a compare current, the drain current being larger or smaller than the compare current indicative of a stored logic state in the FET.

11. A method of interacting with a ferroelectric field effect transistor (FET) having a gate, source, drain, substrate, and a ferroelectric layer, the method comprising:

(a) applying a negative voltage to the gate and ground potential to the source, drain, and substrate, the negative voltage having a magnitude at least equal to a coercive voltage of the FET, and

(b) applying a positive voltage to the gate and ground potential to the substrate, the positive voltage applied to the gate at least equal to a coercive voltage of the FET; and

(c) selectively applying either a positive voltage or ground potential to each of the source and the drain to write a logic state to the FET, the positive voltage applied to the drain about equal to the positive voltage applied to the gate, the positive voltage applied to the source at least equal to the positive voltage applied to the gate.

12. A method for interacting with a selected ferroelectric field effect transistor (FET) in an array of ferroelectric FETs, each ferroelectric FET in the array having a gate, source, drain, substrate, and ferroelectric layer, the array arranged in rows and columns, the gate of each ferroelectric FETs in the same row coupled to a word line, the source of each ferroelectric FETs in the same row coupled to a source line, the drain of each ferroelectric FETs in the same column coupled to a bit line, the method comprising:

(a) applying a negative voltage to the word line of the selected FET and ground potential to the source line, bit line, and substrate of the selected FET, the negative voltage having a magnitude at least equal to a coercive voltage of the FET;

(b) applying a positive voltage to the word line of the selected FET and ground potential to the substrate of the selected FET, the positive voltage applied to the word line having a magnitude at least equal to the coercive voltage; and

(c) selectively applying either a positive voltage or a ground potential to each of the source line and bit line of the selected FET to write a logic state to the selected FET, the positive voltage applied to the source line having a magnitude at least equal to the coercive voltage, the positive voltage applied to the bit line having a magnitude about equal to the magnitude of the positive voltage applied to the word line.