High speed wireless OFDM transceiver modem

• US 6,760,300 B1
• Filed: 02/16/2000
• Issued: 07/06/2004
• Est. Priority Date: 02/17/1999
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: IMEC International, SAIT Devlonics
• Inventors: Eberle, Wolfgang, Van der Perre, Liesbet, Thoen, Steven, Gyselinckx, Bert, Engels, Mark
• Primary Examiner(s): Hsu, Alpus H.
• Assistant Examiner(s): TRAN, THIEN D
• Application Number:
  US09/505,228
• Time in Patent Office: 1,602 Days
• Field of Search: 370/203, 370/319, 370/343, 370/344, 370/210, 370/311, 375/240.18, 375/260, 375/130, 375/131, 375/144, 375/145, 375/146, 375/147, 455/38.3, 455/343, 379/406.13
• US Class Current: 370/210
• CPC Class Codes: H04L 25/0226 sounding signals per se
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 27/2605 Symbol extensions, e.g. Zero Tail, Unique Word [UW]
• CPC Class Codes: H04L 27/2613 Structure of the reference signals
• CPC Class Codes: H04L 27/2657 Carrier synchronisation
• CPC Class Codes: H04L 27/2662 Symbol synchronisation
• CPC Class Codes: H04L 5/0048 Allocation of pilot signals, i.e. of signals known to the receiver

Abstract

An apparatus for receiving and/or transmitting signals using orthogonal frequency division multiplexing, said apparatus being adapted for outputting a first output signal, comprising:

a time synchronisation circuit, being adapted for determination of control information from a first signal, said first signal comprising at least of a first part being a non-orthogonal frequency division multiplexing signal and a second part being an orthogonal frequency division multiplexing signal, said determination of control information exploiting said first part of said first signal;

said time synchronisation circuit, further being adapted for converting said second part of said first signal into a second signal, being in time domain representation;

a transformation circuit at least converting said second signal into a third signal, being in frequency domain representation;

a first frequency domain circuit, at least converting said third signal into said first output signal; and

said second signal and said second part of said first signal being orthogonal frequency division multiplexing signals.

Claims

1. An apparatus for receiving and/or transmitting signals using orthogonal frequency division multiplexing, said apparatus being adapted for outputting a first output signal, comprising:

a time synchronisation circuit, being adapted for determination of control information from a first signal in the time domain representation, said first signal comprising at least of a first part being a non-orthogonal frequency division multiplexing signal and a second part being an orthogonal frequency division multiplexing signal, said determination of control information exploiting said first part of said first signal;

said time synchronisation circuit, further being adapted for converting said second part of said first signal into a second signal, being in time domain representation;

a transformation circuit at least converting said second signal into a third signal, being in frequency domain representation, wherein said frequency domain representations are characterised by a set of carriers, and wherein said transformation circuit comprises a cascade of a fast Fourier transform circuit and a symbol reordering circuit, and said fast Fourier transform circuit performs either a fast Fourier transformation or an inverse fast Fourier transformation;

a first frequency domain circuit, at least converting said third signal into said first output signal; and

said second signal and said second part of said first signal being orthogonal frequency division multiplexing signals.

2. The apparatus for receiving and/or transmitting signals as recited in claim 1, wherein said determination of control information comprises of determination of signal level information.

3. The apparatus for receiving and/or transmitting signals as recited in claim 1, wherein said determination of control information comprises of estimation of the carrier offset;

and said conversion in said time synchronisation circuit comprises of compensation of said carrier offset.

4. The apparatus for receiving and/or transmitting signals as recited in claim 1, wherein said determination of control information comprises of extraction of timing information.

5. The apparatus for receiving and/or transmitting signals as recited in claim 1, wherein said conversion in said time synchronisation circuit comprises of removal of a guard interval.

6. The apparatus for receiving and/or transmitting signals as recited in claim 1, further being adapted for outputting a second output signal and inputting a second input signal, comprising:

transmission means transmitting said fifth signal as said second output signal;

receiving means receiving said second input signal as said first signal; and

said second output signal, being an orthogonal frequency division multiplexing signal.

7. The apparatus for receiving and/or transmitting signals as recited in claim 1, wherein said second frequency domain circuit is assigning bits of said first input signal to the carriers of the frequency domain representation of said fourth signal.

8. The apparatus for receiving and/or transmitting signals as recited in claim 7, wherein said first frequency domain circuit comprising of a cascade of an equalisation circuit and a demapping circuit;

and said demapping circuit is extracting bits from the carriers of the frequency domain representation of the equalised third signal.

9. The apparatus for receiving and/or transmitting signals as recited in claim 7, wherein the amount of carriers in said set of carriers being programmable.

10. The apparatus for receiving and/or transmitting signals as recited in claim 1, wherein part of said carriers being zero carriers and the amount of zero carriers being programmable.

11. The apparatus for receiving and/or transmitting signals as recited in claim 7, wherein said second frequency domain circuit performs spreading;

and the amount of spreading and the spreading code being programmable.

12. The apparatus for receiving and/or transmitting signals as recited in claim 1, wherein inverse fast Fourier transform of said carriers of said frequency domain representations, results in orthogonal frequency division multiplexing symbols;

said symbol reordering circuit, being able to introduce a guard interval in the inverse fast Fourier transformed fourth signal and to reorder the orthogonal frequency division multiplexing symbol in time domain representation of said inverse fast Fourier transformed fourth signal.

13. The apparatus for receiving and/or transmitting as recited in claim 12, wherein said reordering is a first step for despreading.

14. The apparatus for receiving and/or transmitting signals as recited in claim 12, wherein said symbol reordering circuit, with a third input signal and a third output signal, is comprising:

a first and a second memory circuit;

a demultiplexer with as input signal said third input signal and two demultiplexer output signals, each of said demultiplexer output signals being connected to one of said memory circuits; and

a multiplexer with two multiplexer input signals and as multiplexer output signal said third output signal, each of said multiplexer input signals being connected to one of said memory circuits.

15. The apparatus for receiving and/or transmitting signals as recited in claim 12, wherein the length of said guard interval being programmable.

16. An apparatus for receiving and/or transmitting signals using orthogonal frequency division multiplexing, said apparatus being adapted for outputting a first output signal and inputting a first input signal, comprising:

a time synchronisation circuit at least converting a first signal into a second signal, being in time domain representation;

a transformation circuit at least converting said second signal into a third signal, being in frequency domain representation;

a first frequency domain circuit, at least converting said third signal into said first output signal;

a second frequency domain circuit converting said first input signal into a fourth signal, being in a frequency domain representation, wherein said frequency domain representations are characterised by a set of carriers, and said second frequency domain circuit is assigning bits of said first input signal to the carriers of the frequency domain representation of said fourth signal, and wherein said transformation circuit comprises a cascade of a fast Fourier transform circuit and a symbol reordering circuit, and said fast Fourier transform circuit performs either a fast Fourier transformation or an inverse fast Fourier transformation;

said transformation circuit, further being adapted for converting said fourth signal into a fifth signal, being in a time domain representation; and

said second signal, said fifth signal and part of said first signal, being orthogonal frequency division multiplexing signals.

17. The apparatus for receiving and/or transmitting signals as recited in claim 16, further being adapted for outputting a second output signal and inputting a second input signal, comprising:

transmission means transmitting said fifth signal as said second output signal;

receiving means receiving said second input signal as said first signal; and

said second output signal, being an orthogonal frequency division multiplexing signal.

18. The apparatus for receiving and/or transmitting signals as recited in claim 16, wherein said first frequency domain circuit comprising of a cascade of an equalisation circuit and a demapping circuit;

and said demapping circuit is extracting bits from the carriers of the frequency domain representation of the equalised third signal.

19. The apparatus for receiving and/or transmitting signals as recited in claim 16, wherein inverse fast Fourier transform of said carriers of said frequency domain representations, results in orthogonal frequency division multiplexing symbols;

said symbol reordering circuit, being able to introduce a guard interval in the inverse fast Fourier transformed fourth signal and to reorder the orthogonal frequency division multiplexing symbol in time domain representation of said inverse fast Fourier transformed fourth signal.

20. The apparatus for receiving and/or transmitting as recited in claim 19, wherein said reordering is a first step for despreading.

21. The apparatus for receiving and/or transmitting signals as recited in claim 19, wherein said symbol reordering circuit, with a third input signal and a third output signal, is comprising:

a first and a second memory circuit;

a demultiplexer with as input signal said third input signal and two demultiplexer output signals, each of said demultiplexer output signals being connected to one of said memory circuits; and

a multiplexer with two multiplexer input signals and as multiplexer output signal said third output signal, each of said multiplexer input signals being connected to one of said memory circuits.

22. The apparatus for receiving and/or transmitting signals as recited in claim 19, wherein the length of said guard interval being programmable.

23. The apparatus for receiving and/or transmitting signals as recited in claim 16, wherein the amount of carriers in said set of carriers being programmable.

24. The apparatus for receiving and/or transmitting signals as recited in claim 16, wherein part of said carriers being zero carriers and the amount of zero carriers being programmable.

25. The apparatus for receiving and/or transmitting signals as recited in claim 16, wherein said second frequency domain circuit performs spreading;

and the amount of spreading and the spreading code being programmable.

26. An apparatus for receiving and/or transmitting signals using orthogonal frequency division multiplexing, said apparatus being adapted for outputting a first output signal, comprising:

a time synchronisation circuit, being adapted for determination of control information from a first signal in the time domain representation, said first signal comprising at least of a first part being a non-orthogonal frequency division multiplexing signal and a second part being an orthogonal frequency division multiplexing signal, said determination of control information exploiting said first part of said first signal;

said time synchronisation circuit, further being adapted for converting said second part of said first signal into a second signal, being in time domain representation;

a transformation circuit at least converting said second signal into a third signal, being in frequency domain representation;

a first frequency domain circuit, at least converting said third signal into said first output signal; and

said second signal and said second part of said first signal being orthogonal frequency division multiplexing signals;

wherein said time synchronisation circuit, further comprises;

a timing synchronisation circuit;

a signal level control circuit;

a carrier offset estimation circuit;

a carrier offset compensation circuit;

a fourth input signal being first input signals of said circuits;

the output signal of said signal level control circuit being a second input signal of said timing synchronisation circuit;

the output signal of said timing synchronisation circuit being a second input signal of said carrier offset estimation circuit;

the output signal of said carrier offset estimation circuit being a second input signal of said carrier offset compensation circuit; and

the output signal of said carrier offset compensation circuit being a fourth output signal.

27. An apparatus for receiving and/or transmitting signals using orthogonal frequency division multiplexing, said apparatus being adapted for outputting a first output signal and inputting a first input signal, comprising:

a time synchronisation circuit at least converting a first signal into a second signal, being in time domain representation;

a transformation circuit at least converting said second signal into a third signal, being in frequency domain representation;

a first frequency domain circuit, at least converting said third signal into said first output signal;

a second frequency domain circuit converting said first input signal into a fourth signal, being in a frequency domain representation;

said transformation circuit, further being adapted for converting said fourth signal into a fifth signal, being in a time domain representation; and

said second signal, said fifth signal and part of said first signal, being orthogonal frequency division multiplexing signals;

wherein said time synchronisation circuit has a fourth input signal and a fourth output signal, and further comprises;

a timing synchronisation circuit;

a signal level control circuit;

a carrier offset estimation circuit;

a carrier offset compensation circuit;

a fourth input signal being first input signals of said circuits;

the output signal of said signal level control circuit being a second input signal of said timing synchronisation circuit;

the output signal of said timing synchronisation circuit being a second input signal of said carrier offset estimation circuit;

the output signal of said carrier offset estimation circuit being a second input signal of said carrier offset compensation circuit; and

the output signal of said carrier offset compensation circuit being a fourth output signal.

28. An apparatus for receiving and/or transmitting signals using orthogonal frequency division multiplexing, said apparatus being adapted for outputting a first output signal, comprising:

a time synchronisation circuit, being adapted for determination of control information from a first signal in the time domain representation, said first signal comprising at least of a first part being a non-orthogonal frequency division multiplexing signal and a second part being an orthogonal frequency division multiplexing signal, said determination of control information exploiting said first part of said first signal;

said time synchronisation circuit, further being adapted for converting said second part of said first signal into a second signal, being in time domain representation;

a transformation circuit at least converting said second signal into a third signal, being in frequency domain representation;

a first frequency domain circuit, at least converting said third signal into said first output signal; and

said second signal and said second part of said first signal being orthogonal frequency division multiplexing signals;

wherein said transformation circuit comprises a cascade of a N-point fast Fourier transform circuit with N an integer and a symbol reordering circuit; and

said N-point fast Fourier transform circuit performs either a fast Fourier transformation or a inverse fast Fourier transformation.

29. The apparatus for receiving and/or transmitting signals as recited in claim 28, wherein said integer N being programmable.

30. An apparatus for receiving and/or transmitting signals using orthogonal frequency division multiplexing, said apparatus being adapted for outputting a first output signal and inputting a first input signal, comprising:

a time synchronisation circuit at least converting a first signal into a second signal, being in time domain representation;

a transformation circuit at least converting said second signal into a third signal, being in frequency domain representation;

a first frequency domain circuit, at least converting said third signal into said first output signal;

a second frequency domain circuit converting said first input signal into a fourth signal, being in a frequency domain representation;

said transformation circuit, further being adapted for converting said fourth signal into a fifth signal, being in a time domain representation; and

said second signal, said fifth signal and part of said first signal, being orthogonal frequency division multiplexing signals;

wherein said transformation circuit comprises a cascade of a N-point fast Fourier transform circuit with N an integer and a symbol reordering circuit; and

said N-point fast Fourier transform circuit performs either a fast Fourier transformation or a inverse fast Fourier transformation.

31. The apparatus for receiving and/or transmitting signals as recited in claim 30, wherein said integer N being programmable.

32. A method for communicating data between a transmission circuit and a receiving circuit using orthogonal frequency division multiplexing, said method comprising the steps of:

sending a training signal with said transmission circuit;

said training signal being a non-orthogonal frequency division multiplexing signal;

sending a data signal with said transmission circuit, said data signal at least comprising of said data modulated by said transmission circuit with orthogonal frequency division multiplexing;

determining in said receiving circuit control information from said training signal by using first time domain operations;

receiving said modulated data by said transmission circuit; and

demodulating in said receiving circuit said received modulated data;

wherein said training signal comprises;

a first sequence of samples with adjustable length, exploited for determining timing synchronisation information;

a reference sequence of reference samples with adjustable length, exploited for carrier offset estimation; and

said data signal comprises of;

an equalisation sequence of equalisation samples with adjustable length, exploited for channel estimation;

said modulated data;

and wherein said first sequence comprises a plurality of different subsequences;

the ordering of said subsequences in said first sequence, representing a code;

said subsequences, being exploited for determining relative timing synchronisation information; and

said ordering of said subsequences, being exploited for determining absolute timing information.

33. The method as recited in claim 32, wherein said first sequence comprises of:

a first subsequence, exploited for determining relative timing synchronisation information;

a second subsequence; and

said method exploiting the transition from the first to the second subsequence for determining absolute timing information.

34. The method as recited in claim 33, wherein said subsequences are Pseudo Noise sequences.

35. The method as recited in claim 33, wherein said first and second subsequence are equal up to the sign-bit.

36. The method as recited in claim 32, wherein said subsequences are Pseudo Noise sequences.

37. A The method as recited in claim 32, wherein said data signal is appended to said training signal.

38. The method as recited in claim 32, further exploiting said control information during demodulation.

39. The method as recited in claim 32, wherein said demodulation further comprises the steps of:

performing second time domain operations on said data signal;

thereafter converting said data signal from a time domain representation into a frequency domain representation;

thereafter performing frequency domain operations on said data signal; and

exploiting said control information during said second time domain operations.

40. The method as recited in claim 39, wherein said second time domain operations at least comprise of carrier offset compensation and guard interval removal.

41. The method as recited in claim 39, wherein said frequency domain operations at least comprise of equalising and extracting bits from said data signal in frequency domain representation.

42. The method as recited in claim 39, wherein said conversion of said data signal from time to frequency domain representation is a fast Fourier transformation.